Patents by Inventor Toshiyuki Enda
Toshiyuki Enda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11316097Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.Type: GrantFiled: August 26, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Taichi Igarashi, Tadaomi Daibou, Junichi Ito, Tadashi Kai, Shogo Itai, Toshiyuki Enda
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Publication number: 20210296568Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, and a second wiring extending in a second direction that intersects the first direction. A memory cell is between the first wiring and the second wiring and includes a resistive memory element and a switching element that are connected in series between the first wiring and the second wiring. An insulating region surrounds side surfaces of the memory cell. The insulating region includes a first insulating part adjacent to a side surface of the resistive memory element and a second insulating part adjacent to a side surface of the switching element. The second insulating part has a higher thermal conductivity than the first insulating part.Type: ApplicationFiled: August 26, 2020Publication date: September 23, 2021Inventors: Taichi IGARASHI, Tadaomi DAIBOU, Junichi ITO, Tadashi KAI, Shogo ITAI, Toshiyuki ENDA
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Patent number: 10847223Abstract: A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va>Vd>Vb and Va>Vd>Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.Type: GrantFiled: August 30, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Naoki Kusunoki, Toshiyuki Enda, Hiroki Tokuhira, Takayuki Miyazaki
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Publication number: 20200294590Abstract: A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va>Vd>Vb and Va>Vd>Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.Type: ApplicationFiled: August 30, 2019Publication date: September 17, 2020Inventors: Naoki KUSUNOKI, Toshiyuki ENDA, Hiroki TOKUHIRA, Takayuki MIYAZAKI
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Patent number: 9030881Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.Type: GrantFiled: August 8, 2013Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Tokuhira, Tsukasa Nakai, Hiroyoshi Tanimoto, Masaki Kondo, Toshiyuki Enda, Nobutoshi Aoki
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Patent number: 8964459Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.Type: GrantFiled: February 28, 2013Date of Patent: February 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsukasa Nakai, Takashi Izumida, Jyunichi Ozeki, Masaki Kondo, Toshiyuki Enda, Nobutoshi Aoki
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Publication number: 20140254276Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.Type: ApplicationFiled: August 8, 2013Publication date: September 11, 2014Inventors: Hiroki TOKUHIRA, Tsukasa NAKAI, Hiroyoshi TANIMOTO, Masaki KONDO, Toshiyuki ENDA, Nobutoshi AOKI
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Patent number: 8809931Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.Type: GrantFiled: March 20, 2013Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsukasa Nakai, Nobutoshi Aoki, Takashi Izumida, Masaki Kondo, Toshiyuki Enda
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Patent number: 8633535Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.Type: GrantFiled: June 9, 2011Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kouji Matsuo, Toshiyuki Enda, Nobutoshi Aoki, Toshihiko Iinuma
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Publication number: 20130248965Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.Type: ApplicationFiled: March 20, 2013Publication date: September 26, 2013Inventors: Tsukasa NAKAI, Nobutoshi AOKI, Takashi IZUMIDA, Masaki KONDO, Toshiyuki ENDA
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Publication number: 20130250670Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.Type: ApplicationFiled: February 28, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsukasa NAKAI, Takashi IZUMIDA, Jyunichi OZEKI, Masaki KONDO, Toshiyuki ENDA, Nobutoshi AOKI
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Patent number: 8165852Abstract: A simulation apparatus of semiconductor device includes a first calculator, a second calculator, a third calculator, a fourth calculator, and a controller. The first calculator applies a voltage to an area which functions as a virtual electrode, and setting a pseudo-Fermi level of a first carrier in the area functioning as the virtual electrode to calculate a first carrier density. The second calculator analyzes continuous equation of a second carrier to calculate a second carrier density. The third calculator uses the first carrier density as a function of an electrostatic potential, and solving a first equation of the function and a Poisson's equation to calculate an electrostatic potential and the first carrier density expressed by the function. The fourth calculator calculates a current density of the first carrier to calculate a current flowing. The controller controls the voltage applied to the virtual electrode.Type: GrantFiled: September 21, 2009Date of Patent: April 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Toshiyuki Enda
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Publication number: 20110303958Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.Type: ApplicationFiled: June 9, 2011Publication date: December 15, 2011Inventors: Kouji MATSUO, Toshiyuki Enda, Nobutoshi Aoki, Toshihiko Iinuma
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Patent number: 7956408Abstract: A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a seType: GrantFiled: January 28, 2008Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Enda, Hirosyoshi Tanimoto, Takashi Izumida
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Patent number: 7764542Abstract: A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.Type: GrantFiled: April 2, 2008Date of Patent: July 27, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Edahiro, Takuya Futatsuyama, Toshiyuki Enda
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Patent number: 7755134Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.Type: GrantFiled: June 20, 2007Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Nobutoshi Aoki, Masaru Kidoh, Ryota Katsumata, Masaki Kondo, Naoki Kusunoki, Toshiyuki Enda, Sanae Ito, Hiroyoshi Tanimoto, Hideaki Aochi, Akihiro Nitayama, Riichiro Shirota
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Publication number: 20100169061Abstract: A simulation apparatus of semiconductor device includes a first calculator, a second calculator, a third calculator, a fourth calculator, and a controller. The first calculator applies a voltage to an area which functions as a virtual electrode, and setting a pseudo-Fermi level of a first carrier in the area functioning as the virtual electrode to calculate a first carrier density. The second calculator analyzes continuous equation of a second carrier to calculate a second carrier density. The third calculator uses the first carrier density as a function of an electrostatic potential, and solving a first equation of the function and a Poisson's equation to calculate an electrostatic potential and the first carrier density expressed by the function. The fourth calculator calculates a current density of the first carrier to calculate a current flowing. The controller controls the voltage applied to the virtual electrode.Type: ApplicationFiled: September 21, 2009Publication date: July 1, 2010Inventor: Toshiyuki ENDA
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Patent number: 7539055Abstract: A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.Type: GrantFiled: June 14, 2007Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunoki, Nobutoshi Aoki, Fumitaka Arai, Riichiro Shirota
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Patent number: 7528447Abstract: A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.Type: GrantFiled: April 5, 2006Date of Patent: May 5, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunoki, Nobutoshi Aoki, Fumitaka Arai, Riichiro Shirota
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Patent number: 7459748Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.Type: GrantFiled: October 16, 2006Date of Patent: December 2, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Fumitaka Arai, Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunoki, Nobutoshi Aoki, Makoto Mizukami, Kiyotaka Miyano, Ichiro Mizushima