Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and first and second output terminals, a first differential amplifier circuit including a first drive cascode circuit and a first tail current source amplifies first and second input signals supplied to the first and second input terminals and transmits the amplified first and second input signals to the second and first output terminals, respectively, and a second differential amplifier circuit including a second drive cascode circuit and a second tail current source amplifies the first and second input signals. Also, a first circuit is connected between the first output terminal and the second power supply terminal so that the first circuit serves as an input-stage load or an output drive circuit, and a second circuit is connected between the second output terminal and the second power supply terminal so that the second circuit serves as an input-stage load or an output drive circuit.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped NOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and first and second output terminals, a first differential amplifier circuit including a first drive cascode circuit and a first tail current source amplifies first and second input signals supplied to the first and second input terminals and transmits the amplified first and second input signals to the second and first output terminals, respectively, and a second differential amplifier circuit including a second drive cascode circuit and a second tail current source amplifies the first and second input signals. Also, a first circuit is connected between the first output terminal and the second power supply terminal so that the first circuit serves as an input-stage load or an output drive circuit, and a second circuit is connected between the second output terminal and the second power supply terminal so that the second circuit serves as an input-stage load or an output drive circuit.

Abstract: There is provided signal node for receiving a signal, a reference node having a reference voltage, an operational amplifier having an input terminal and an output terminal, a first capacitor, and a second capacitor equivalent in capacitance to the first capacitor connectable by a combination of switches responsive to a control signal for connecting the first capacitor between the signal node and the reference node and the second capacitor between the input terminal and the output terminal of the operational amplifier, and to an inverted signal of the control signal for connecting the second capacitor between the signal node and the reference node and the first capacitor between the input terminal and the output terminal of the operational amplifier, the control signal and the inverted signal thereof being complementary to each other so as to be alternately effective.

Abstract: A cascode circuit includes a source-grounded input NMOS transistor having a gate connected to an input terminal and a drain connected through an output NMOS transistor to an output terminal. An amplification circuit is constructed by a gate-grounded third NMOS transistor having a source connected to the drain of the input transistor, a current mirror circuit consisting of PMOS transistors having an input current path connected to a drain of the third transistor, and a current source connected to an output current path of the constant mirror circuit as a load. An output from the amplification circuit is fed back to a gate of the second transistor. With this arrangement, the cascode circuit can maintain a high output impedance until a minimum output signal voltage reaches around 0.5 V, and can also have a minimum working supply voltage of about 2 V, and at the same time, a circuit construction suitable for IC in the CMOS process.

Abstract: A voltage-to-current conversion circuit is disclosed which includes a MOS transistor of a source-grounded type having a gate connected to an input terminal, an output circuit producing an output current at an output terminal in response to a drain current of the transistor, and a control circuit maintaining the drain voltage of the transistor to such a value that has the transistor operates in a non-saturation (triode) region.