Abstract: In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance.

Abstract: A pipeline circuit is capable of adjusting the timing of data, in a data processing system for ensuring processing, even if the input timings of different data are irregular or the input data are invalid. This is achieved by generating a selection signal, which is input to a data holding circuit. The selection signal determines the particular register in which a datum is stored. The value of the selection signal is determined by an input indicating signal, which indicates whether a particular datum is valid or invalid. When the data is valid the selection signal is shifted to the next value, indicating the next higher register, and when the data is invalid the selection signal maintains the value it had for the previous datum.

Abstract: In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left between two adjacent ones of the data elements, a request control circuit (40) decides an element number in each cycle with reference to a logical distance (D) determined by the interval. The memory can be accessed in each cycle by a plurality of real addresses which are equal in number to the element number and which are calculated from the logical distance and the preselected logical address. Preferably, an address translation unit (80) is supplied with the preselected logical address and a part of the logical distance to produce a plurality of consecutive real page addresses (RPE and RPO) one of which corresponds to the preselected logical address. An address generator (50) produces a predetermined number of local logical addresses (EA.sub.0 .about.EA.sub.