Patents by Inventor Toshiyuki Hisamura

Toshiyuki Hisamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermal enablement of dies with impurity gettering
    Patent number: 11488887
    Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 1, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Boon Y. Ang, Toshiyuki Hisamura, Suresh Parameswaran, Scott McCann, Hoa Lap Do
  • Single mask set used for interposer fabrication of multiple products
    Patent number: 9915869
    Abstract: A method for fabricating an interposer wafer includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 13, 2018
    Assignee: XILINX, INC.
    Inventor: Toshiyuki Hisamura
  • Oversized interposer
    Patent number: 8957512
    Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Xilinx, Inc.
    Inventor: Toshiyuki Hisamura
  • OVERSIZED INTERPOSER
    Publication number: 20130333921
    Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: XILINX, INC.
    Inventor: Toshiyuki Hisamura