Abstract: An information processing apparatus includes: a memory configured to store correction information for performing distortion correction on an image; and a processor coupled to the memory and configured to: based on a characteristic of each imaging circuit of a plurality of imaging circuits that captures different images, group two or more imaging circuits for each of which determination is made that distortion correction is capable of being performed on an image based on the correction information among the plurality of imaging circuits; and perform distortion correction on an image captured by each imaging circuit of the two or more imaging circuits that are grouped, based on the correction information stored in the memory.

Abstract: A processor includes issuing units to issue a read access request to a storage, a cache including banks capable of holding first data divided from data read from the storage, a switch interconnecting the issuing units and the banks, and a data distribution unit disposed between the issuing units and the switch. The switch outputs one of read access requests to a bank that is a read target, when each of read target data of the read access requests issued from the issuing units is one of second data included in the first data, and the first data read from the bank is output to the data distribution unit. The data distribution unit outputs each of the second data, divided from the first data received from the switch, in parallel to an issuing unit that is an originator of the read access request.

Abstract: A calculator includes a processing core and a cache. The cache includes a data memory that holds data transferred from a main memory and a cache controller that controls transfer of data between the main memory and the data memory. The cache controller is configured to calculate, upon occurrence of a cache miss, a cycle count requested for arithmetic processing on one unit amount of data based on a cache miss occurrence interval and a memory access latency requested, and update a prefetch distance based on the calculated cycle count and the memory access latency, the prefetch distance indicating a relative distance on the main memory between a location from which the one unit amount of data transferred from the main memory due to the cache miss and a location from which a next one unit amount of data is to be prefetched.

Abstract: A calculator includes a processing core and a cache. The cache includes a data memory that holds data transferred from a main memory and a cache controller that controls transfer of data between the main memory and the data memory. The cache controller is configured to calculate, upon occurrence of a cache miss, a cycle count requested for arithmetic processing on one unit amount of data based on a cache miss occurrence interval and a memory access latency requested, and update a prefetch distance based on the calculated cycle count and the memory access latency, the prefetch distance indicating a relative distance on the main memory between a location from which the one unit amount of data transferred from the main memory due to the cache miss and a location from which a next one unit amount of data is to be prefetched.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.

Abstract: A compiler device includes: a processor configured to: when a first register is allocated to first and second spill instructions, which refer to same data in a memory, of an instruction sequence and to a first section between the first and second spill instructions, search for a second register that is a candidate allocated to the first section instead of the first register; when a second section allocated with the second register and the first section do not overlap, allocate the second register to the first section instead of the first register; when the first and second sections overlap, allocate a third register to the second section instead of the second register, and then allocate the second register to the first section instead of the first register; and thereafter, delete an instruction executed later than the other instruction of the first and second spill instructions.

Abstract: A compiler device includes: a processor configured to: when a first register is allocated to first and second spill instructions, which refer to same data in a memory, of an instruction sequence and to a first section between the first and second spill instructions, search for a second register that is a candidate allocated to the first section instead of the first register; when a second section allocated with the second register and the first section do not overlap, allocate the second register to the first section instead of the first register; when the first and second sections overlap, allocate a third register to the second section instead of the second register, and then allocate the second register to the first section instead of the first register; and thereafter, delete an instruction executed later than the other instruction of the first and second spill instructions.

Abstract: An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.

Abstract: An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.