Patents by Inventor Toshiyuki Isami

Toshiyuki Isami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395423
    Abstract: A producing method of a handle wafer for a bonded wafer produced by bonding an active wafer and the handle wafer through an insulation film includes: preparing a handle wafer body made from a monocrystalline silicon wafer; forming an oxide film on the handle wafer body; depositing a polycrystalline silicon layer on the oxide film; forming a protective oxide film on a surface of the polycrystalline silicon layer; and polishing to remove the protective oxide film and polishing the polycrystalline silicon layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: December 7, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Naoya NONAKA, Daisuke HIEDA, Hiroaki ISHIZAKI, Toshiyuki ISAMI, Koudai MOROIWA
  • Patent number: 8906777
    Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: December 9, 2014
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuhiro Iriguchi, Toshiyuki Isami, Kouhei Kawano
  • Patent number: 8420514
    Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration to execute a baking treatment. After a surface layer of the silicon crystal substrate is then polished up to a predetermined amount, a silicon epitaxial layer is grown by a CVD method. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: April 16, 2013
    Assignee: Sumco Corporation
    Inventors: Tadashi Kawashima, Masahiro Yoshikawa, Akira Inoue, Yoshiya Yoshida, Kazuhiro Iriguchi, Toshiyuki Isami
  • Publication number: 20120112319
    Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration to execute a baking treatment. After a surface layer of the silicon crystal substrate is then polished up to a predetermined amount, a silicon epitaxial layer is grown by a CVD method. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.
    Type: Application
    Filed: July 1, 2010
    Publication date: May 10, 2012
    Applicant: SUMCO CORPORATION
    Inventors: Tadashi Kawashima, Masahiro Yoshikawa, Akira Inoue, Yoshiya Yoshida, Kazuhiro Iriguchi, Toshiyuki Isami
  • Publication number: 20090197359
    Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.
    Type: Application
    Filed: January 29, 2009
    Publication date: August 6, 2009
    Inventors: Kazuhiro Iriguchi, Toshiyuki Isami, Kouhei Kawano