Abstract: A semiconductor memory cell of one transistor - one capacitor memory cell type in which a storage capacitor of a first memory cell is formed on a switching transistor of a second memory cell as well as on a switching transistor of the first memory cell, and a storage capacitor of the second memory cell is formed on the switching transistor of the first memory cell as well as on the switching transistor of the second memory cell.

Abstract: For reduction in occupation area, there is provided a complementary field effect transistor consisting of a n-channel MIS type field effect transistor formed along a side wall of a p-type silicon substrate and a p-channel MIS type field effect transistor formed along a side wall of an n-type well in the p-type silicon substrate, and both of the side wall of the silicon substrate and the side wall of the n-type well define a groove where a conductive material is deposited to provide an interconnection between the n-type and p-type MIS type field effect transistors and another complementary field effect transistor.

Abstract: For preventing a field effect transistor from the short-channel effects, there is disclosed a field effect transistor comprising a channel region and source/drain regions deviating from the central portion of the channel region in the lateral direction of the field effect transistor, a gate electrode covered with an insulating film intervenes between the source/drain regions, so that the channel length is increased in length.