Abstract: In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A process of cleaning debris (24) from a partially-sawn semiconductor wafer (10). The method of the present invention includes cleaning a partially fabricated wafer (12) that may have fabricated on it a micromechanical device (16) which can be easily damaged by particles (24) generated by the partial-saw process, such as oxide particles. The present invention includes cleaning the partially-sawn wafer with a solution including diluted hydrofluoric acid and an alkyl glycol. Clean-up using this solution accomplishes two goals. First, it removes debris including oxide particles on the wafer surface and in the kerfs (22), and second, reduces the depth of damage in the surface (26) of a CMOS layer (14) proximate the kerf (22) which has been determined to be a source of particles generated after a wafer cleanup process. A subsequent megasonic process is utilized to acoustically vibrate the wafer while bathed in deionized water to further remove any other particles.

Abstract: A method for attaining a uniform roughening of a silicon semiconductor surface with a microscopic amount of roughness at the .ANG. level, wherein the amount of roughness may be accurately and precisely controlled without complicating the manufacturing processes and increasing the manufacturing cost, and regardless of the shape of the silicon surface area of the substrate. The substrate with the silicon surface area is immersed in a cleansing solution, such as SC1 for example, containing a metallic substance, such as Fe, Ni, Cu, Zn, Al, and Cr, for example, at the ppb level to wash the surface. Then, a silicon oxide film uniformly containing the metallic substance is formed on the silicon surface of the substrate after drying, and isotropic etching is performed on the surface of the substrate formed with the silicon oxide film by etching Si from the silicon oxide film at a high ratio of selectivity to form microscopic irregularities.

Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Abstract: An improved support post (16, 23, 25) for micro-mechanical devices (10). A via (34a) that defines the outer surface of the support post (16) is etched into a spacer layer (34). An oxide layer (41) is conformally deposited over the spacer layer (34) and into the via (34a), and then etched back to the top surface of the spacer layer (34), leaving a sidewall ring (23a) on the inner surface of the via (34a). Next, a metal layer (61) is deposited over the spacer layer (34) and into the via (34a) so as to cover the sidewall ring (23a). This metal layer (61) is then etched to form a support post stem (23) inside the via (34a). The spacer layer (34) is removed, leaving the support post stem (23) and a sidewall ring (23a) around the stem (23).

Abstract: An improved support post (16, 23, 25) for micro-mechanical devices (10). A via (34a) that defines the outer surface of the support post (16) is etched into a spacer layer (34). An oxide layer (41) is conformally deposited over the spacer layer (34) and into the via (34a), and then etched back to the top surface of the spacer layer (34), leaving a sidewall ring (23a) on the inner surface of the via (34a). Next, a metal layer (61) is deposited over the spacer layer (34) and into the via (34a) so as to cover the sidewall ring (23a). This metal layer (61) is then etched to form a support post stem (23) inside the via (34a). The spacer layer (34) is removed, leaving the support post stem (23) and a sidewall ring (23a) around the stem (23).

Abstract: An improved support post (16, 23, 25) for micro-mechanical devices (10). A via (34a) that defines the outer surface of the support post (16) is etched into a spacer layer (34). An oxide layer (41) is conformally deposited over the spacer layer (34) and into the via (34a), and then etched back to the top surface of the spacer layer (34), leaving a sidewall ring (23a) on the inner surface of the via (34a). Next, a metal layer (61) is deposited over the spacer layer (34) and into the via (34a) so as to cover the sidewall ring (23a). This metal layer (61) is then etched to form a support post stem (23) inside the via (34a). The spacer layer (34) is removed, leaving the support post stem (23) and a sidewall ring (23a) around the stem (23).

Abstract: A semiconductor device having a salicide (self-aligned silicide) configuration and operable as, for example, a dynamic RAM device is fabricated by preparing a semiconductor substrate, forming a layer of silicon in, on or over the semiconductor substrate, forming a layer of a metal on the layer of silicon, the metal silicide layer having a surface portion, and heating the resultant structure in the presence of a reaction ambient containing nitride for forming on the layer of silicon a layer of a metal silicide having a surface portion and nitriding the surface portion to form a nitride layer consisting of a nitride of said metal silicide.