Abstract: An information processing device (30) includes a signal acquisition unit (31), a passive depth estimation unit (34), and a fusion unit (35). The signal acquisition unit (31) extracts, from light reception data, active information indicating a flight time of reference light (PL) and passive information (PI) indicating two-dimensional image information of a subject (SU) obtained from ambient light (EL). The passive depth estimation unit (34) generates passive depth information (PDI) based on the passive information (PI). The fusion unit (35) fuses the passive depth information (PDI) with active depth information (ADI) generated based on the active information to generate depth information (DI) of the subject (SU).

Abstract: In a image processing system for an electrophotographic printer, a density selective circuit selects density data of a pixel to be corrected in response to the black-and-white patterns of surrounding pixels in a line matrix, and a density correction operation circuit outputs a picture signal with corrected density data corrected by the selected density and other density correction coefficients, thereby the toner adhesion amount, i.e., the printing density is made uniform and a clear printed picture without density unevenness can be obtained irrespective of the content of the picture signal.

Abstract: A half tone image processing circuit in which samples of an image signal are compared with elements of a dither matrix to generate a binary image signal, and including a scale reduction circuit for canceling predetermined bits from the binary image signal to effect a reduction in size of an image produced in accordance with the binary image signal. A dither generation circuit sequentially outputs the dither elements in response to a clock signal. During scale reduction, the incrementing of the dither generation circuit is halted when samples are received that correspond to the bits to be canceled, so as to avoid picture quality degradation by maintaining continuity of the dither generation pattern.

Abstract: A digital binarization circuit for image data includes a background level detecting circuit which uses a video signal as a reference input for determining the background level of an image represented by the video signal, and outputs the background level as a first address signal. A character level detecting circuit compares the video signal with a character level in a load decision comparator and loads the video signal as a character level when the signal is less than the reference level, and outputs the character level as a second address signal. A memory circuit ouputs a threshold value stored at an address designated by the first and second address signals to a comparator. The optimum threshold value is outputted among prescribed threshold values stored in the memory circuit. The comparator compares the digitized video signal with the optimum threshold value and outputs a binary signal corresponding to the comparison result.