Abstract: Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

Abstract: Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

Abstract: A switch apparatus of the invention comprises a first input terminal, a second input terminal to which a second input signal having a level lower than a level of the first input signal is supplied, a first switch block for outputting the first input signal supplied from the first input terminal through a plurality of switching elements, a second switch block for outputting the second input signal supplied from the second input terminal through a plurality of switching elements; and a control terminal to which a control signal is supplied wherein the control signal controls the first switch block when outputting the first input signal, and controls the second switch block when outputting the second input signal, wherein the first switch block is configured to have a smaller number of switching elements than that of the second switch block.

Abstract: A power amplifier able to minimize the deterioration of the linearity with respect to fluctuations in ambient temperature, wherein a first terminal of a first resistance element and a first terminal of a second resistance with a temperature coefficient smaller than that of the first resistance element are connected, the connection point is connected to a gate terminal of an FET, a second terminal of the first resistance element is connected to a bias voltage supply terminal, a second terminal of the second resistance element is connected to the ground potential, a drain terminal of the FET is connected to a power source voltage supply terminal, a source terminal is connected to the ground potential, and the FET and the first resistance element are constituted by semiconductor devices formed on the same semiconductor substrate.

Abstract: A switch apparatus of the invention comprises a first input terminal, a second input terminal to which a second input signal having a level lower than a level of the first input signal is supplied, a first switch block for outputting the first input signal supplied from the first input terminal through a plurality of switching elements, a second switch block for outputting the second input signal supplied from the second input terminal through a plurality of switching elements; and a control terminal to which a control signal is supplied wherein the control signal controls the first switch block when outputting the first input signal, and controls the second switch block when outputting the second input signal, wherein the first switch block is configured to have a smaller number of switching elements than that of the second switch block.

Abstract: A power amplifier able to minimize the deterioration of the linearity with respect to fluctuations in ambient temperature, wherein a first terminal of a first resistance element and a first terminal of a second resistance with a temperature coefficient smaller than that of the first resistance element are connected, the connection point is connected to a gate terminal of an FET, a second terminal of the first resistance element is connected to a bias voltage supply terminal, a second terminal of the second resistance element is connected to the ground potential, a drain terminal of the FET is connected to a power source voltage supply terminal, a source terminal is connected to the ground potential, and the FET and the first resistance element are constituted by semiconductor devices formed on the same semiconductor substrate.