Patents by Inventor Toshiyuki Kosaka
Toshiyuki Kosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626323Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: GrantFiled: February 16, 2021Date of Patent: April 11, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata
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Patent number: 11515208Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.Type: GrantFiled: February 17, 2021Date of Patent: November 29, 2022Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
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Publication number: 20210193520Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.Type: ApplicationFiled: February 17, 2021Publication date: June 24, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki KOSAKA, Shunsuke KURACHI
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Publication number: 20210166970Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: ApplicationFiled: February 16, 2021Publication date: June 3, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki KOSAKA, Haruo KAWATA
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Patent number: 10957591Abstract: A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.Type: GrantFiled: February 15, 2019Date of Patent: March 23, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
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Patent number: 10943821Abstract: A method of manufacturing a semiconductor device includes: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: GrantFiled: July 25, 2019Date of Patent: March 9, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata
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Publication number: 20200035551Abstract: A method of manufacturing a semiconductor device includes: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.Type: ApplicationFiled: July 25, 2019Publication date: January 30, 2020Applicant: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki KOSAKA, Haruo KAWATA
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Publication number: 20190259662Abstract: A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) in the secondary surface of the substrate and within the substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion except for the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.Type: ApplicationFiled: February 15, 2019Publication date: August 22, 2019Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki KOSAKA, Shunsuke KURACHI
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Patent number: 10100462Abstract: There is provided a high-tensile synthetic fiber rope having a low percentage elongation, the rope dramatically improving the strength utilization rate of the tensile strength of the synthetic fibers, and ensuring the percentage elongation approximately the same as the percentage elongation of the synthetic fibers used in the rope. The synthetic fiber rope includes a plurality of strands twisted or braided together, each of the strands including: a tubular woven fabric woven with warp and weft yarns made of synthetic fibers; and a core material disposed in the tubular woven fabric, the core material being constituted by a plurality of parallel-bundled yarns made of the synthetic fibers in the tubular woven fabric.Type: GrantFiled: October 23, 2013Date of Patent: October 16, 2018Assignees: OBAMA ROPE MFG., CO., LTD., ASHIMORI INDUSTRY CO., LTD.Inventors: Yuzo Kikuchi, Yoshihiro Kinoshita, Toshiyuki Kosaka, Sosuke Morimoto
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Patent number: 9368405Abstract: A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.Type: GrantFiled: January 29, 2015Date of Patent: June 14, 2016Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki Kosaka, Hiroshi Kawakubo
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Publication number: 20150221554Abstract: A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.Type: ApplicationFiled: January 29, 2015Publication date: August 6, 2015Inventors: Toshiyuki KOSAKA, Hiroshi KAWAKUBO
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Publication number: 20150152594Abstract: There is provided a high-tensile synthetic fiber rope having a low percentage elongation, the rope dramatically improving the strength utilization rate of the tensile strength of the synthetic fibers, and ensuring the percentage elongation approximately the same as the percentage elongation of the synthetic fibers used in the rope. The synthetic fiber rope includes a plurality of strands twisted or braided together, each of the strands including: a tubular woven fabric woven with warp and weft yarns made of synthetic fibers; and a core material disposed in the tubular woven fabric, the core material being constituted by a plurality of parallel-bundled yarns made of the synthetic fibers in the tubular woven fabric.Type: ApplicationFiled: October 23, 2013Publication date: June 4, 2015Applicants: OBAMA ROPE MFG., CO., LTD., ASHIMORI INDUSTRY CO., LTD.Inventors: Yuzo Kikuchi, Yoshihiro Kinoshita, Toshiyuki Kosaka, Sosuke Morimoto
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Patent number: 8563404Abstract: A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).Type: GrantFiled: July 28, 2011Date of Patent: October 22, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Toshiyuki Kosaka
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Patent number: 8563433Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.Type: GrantFiled: July 22, 2011Date of Patent: October 22, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Toshiyuki Kosaka
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Patent number: 8476166Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.Type: GrantFiled: September 29, 2010Date of Patent: July 2, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki Kosaka, Haruo Kawata, Tsutomu Komatani
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Patent number: 8455951Abstract: A semiconductor device includes a substrate having a rectangular shape, and a via hole that has an elliptic shape or a track shape having a linear portion in a long-axis direction of the track shape, a long axis of the elliptic shape or the track shape being arranged in a long-side direction of the substrate.Type: GrantFiled: November 19, 2010Date of Patent: June 4, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Toshiyuki Kosaka
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Publication number: 20120025207Abstract: A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).Type: ApplicationFiled: July 28, 2011Publication date: February 2, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Toshiyuki KOSAKA
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Publication number: 20120028465Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.Type: ApplicationFiled: July 22, 2011Publication date: February 2, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Toshiyuki KOSAKA
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Publication number: 20110084341Abstract: A semiconductor device includes a substrate having a rectangular shape, and a via hole that has an elliptic shape or a track shape having a linear portion in a long-axis direction of the track shape, a long axis of the elliptic shape or the track shape being arranged in a long-side direction of the substrate.Type: ApplicationFiled: November 19, 2010Publication date: April 14, 2011Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Toshiyuki Kosaka
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Publication number: 20110081784Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.Type: ApplicationFiled: September 29, 2010Publication date: April 7, 2011Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Toshiyuki Kosaka, Haruo Kawata, Tsutomu Komatani