Abstract: A wiring substrate is provided. The wiring substrate includes: a core layer in which a gap is formed; and a lamination layer which includes an insulating layer and a wiring layer and which is formed on at least one surface of the core layer. The lamination layer has a thermal expansion coefficient different from that of the core layer. A plurality of mounting regions on which an electronic component is to be mounted are provided on the lamination layer to be spaced from each other. The gap in the core layer is filled with an insulating member having the same material as the insulating layer and surrounds each of the plurality of mounting regions or each of mounting region groups including one or more of the mounting regions.

Abstract: An electronic component mounting device according to the invention includes a bonding head for holding and pressure bonding an electronic component to a mounting substrate, a local stage provided with a support surface formed in an area which is almost equal to or slightly larger than that of a mounting surface of the electronic component and serving to support a pressure bonding force from an antimounting surface of the mounting substrate through the support surface, a length measuring mechanism for measuring a distance between the bonding head and the mounting substrate, thereby calculating a virtual plane in a predetermined mounting position on the mounting substrate, and a tilting and moving mechanism for tilting and moving the bonding head and the local stage, thereby causing a normal of the virtual plane in the mounting position to be coincident with an action line of the pressure bonding force, and the pressure bonding is carried out along the normal.

Abstract: A wiring substrate is provided. The wiring substrate includes: a core layer in which a gap is formed; and a lamination layer which includes an insulating layer and a wiring layer and which is formed on at least one surface of the core layer. The lamination layer has a thermal expansion coefficient different from that of the core layer. A plurality of mounting regions on which an electronic component is to be mounted are provided on the lamination layer to be spaced from each other. The gap in the core layer is filled with an insulating member having the same material as the insulating layer and surrounds each of the plurality of mounting regions or each of mounting region groups including one or more of the mounting regions.

Abstract: An electronic component mounting device according to the invention includes a bonding head for holding and pressure bonding an electronic component to a mounting substrate, a local stage provided with a support surface formed in an area which is almost equal to or slightly larger than that of a mounting surface of the electronic component and serving to support a pressure bonding force from an antimounting surface of the mounting substrate through the support surface, a length measuring mechanism for measuring a distance between the bonding head and the mounting substrate, thereby calculating a virtual plane in a predetermined mounting position on the mounting substrate, and a tilting and moving mechanism for tilting and moving the bonding head and the local stage, thereby causing a normal of the virtual plane in the mounting position to be coincident with an action line of the pressure bonding force, and the pressure bonding is carried out along the normal.

Abstract: A semiconductor device includes: a semiconductor chip connected onto a surface of a printed wiring board in a flip-chip connection; a dam for preventing an outflow of underfill, the dam being provided on the surface of the printed wiring board and surrounding an entire circumference of the semiconductor chip; an external connection terminal for the semiconductor chip, the external connection terminal being provided on the surface of the printed wiring board and arranged outside the dam; a solder resist layer covering the surface of the printed wiring board except for portions for the flip-chip connection and the external connection terminal arrangement; and at least one recess portion being provided in the solder resist layer and within a region between a corner portion of the semiconductor chip and a corner portion of the dam being opposed to the corner portion of the semiconductor chip.

Abstract: A packaging substrate for a semiconductor device includes: a solder resist on a surface of the packaging substrate, the solder resist having a first opening portion for mounting the semiconductor device; and a speed adjusting opening portion for adjusting a flow speed of an underfill resin when the underfill resin is provided, the adjusting section being positioned in vicinity of the first opening portion of the solder resist.

Abstract: In a semiconductor device in which a semiconductor element 10 in which plural electrode terminals 16 are formed along the peripheral edge inside a region of a predetermined width along the peripheral edge excluding the center and the vicinity of the center is mounted on a pad formation surface of a substrate 12 on which pads 14 corresponding to each of the electrode terminals 16 are formed and connection parts 26 between the semiconductor element 10 and the substrate 12 are sealed with an underfill material 24, it is wherein a dam 20 surrounding an inward region 28 is formed so as to separate a connection part region in which the connection parts 26 are present from the inward region 28 inward beyond the connection part region and the connection part region is sealed with the underfill material 24 and plural through holes 22 extending through the substrate 12 are formed inside the inward region 28 of the substrate 12 surrounded by the dam 20.

Abstract: A semiconductor device includes: a semiconductor chip connected onto a surface of a printed wiring board in a flip-chip connection; a dam for preventing an outflow of underfill, the dam being provided on the surface of the printed wiring board and surrounding an entire circumference of the semiconductor chip; an external connection terminal for the semiconductor chip, the external connection terminal being provided on the surface of the printed wiring board and arranged outside the dam; a solder resist layer covering the surface of the printed wiring board except for portions for the flip-chip connection and the external connection terminal arrangement; and at least one recess portion being provided in the solder resist layer and within a region between a corner portion of the semiconductor chip and a corner portion of the dam being opposed to the corner portion of the semiconductor chip.

Abstract: A packaging substrate for a semiconductor device includes: a solder resist on a surface of the packaging substrate, the solder resist having a first opening portion for mounting the semiconductor device; and a speed adjusting opening portion for adjusting a flow speed of an underfill resin when the underfill resin is provided, the adjusting section being positioned in vicinity of the first opening portion of the solder resist.

Abstract: A multichip-module fabrication method includes the step of forming a chip-mounting substrate by forming a bonding layer on a supporting base and by forming one or a plurality of interconnection layers in a stack formation on the bonding layer via insulating layers. This method also includes the step of forming one or a plurality of throughholes extending through the insulating layers to the bonding layer on the chip-mounting substrate. Subsequently, this method separates the supporting base from the chip-mounting substrate by leading a treatment medium which is capable of removing the bonding layer to the bonding layer at least through one or a plurality of the throughholes. Finally, by mounting a semiconductor chip on the chip-mounting substrate, the multichip-module fabrication method is completed.

Abstract: A semiconductor apparatus includes a semiconductor element and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base. The thin-film multilayer interconnection layer has insulating layers and interconnection patterns. The insulating layers and the interconnection patterns are alternately layered. Each of the insulating layers includes a first insulating layer part and a second insulating layer part. A surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of the interconnection patterns is arranged on the surface of the second insulating layer part.

Abstract: A multichip-module fabrication method includes the step of forming a chip-mounting substrate by forming a bonding layer on a supporting base and by forming one or a plurality of interconnection layers in a stack formation on the bonding layer via insulating layers. And this method includes the step of forming one or a plurality of throughholes extending through said insulating layers to said bonding layer on said chip-mounting substrate. And subsequently, this method separates said supporting base from said chip-mounting substrate by leading a treatment medium which is capable of removing said bonding layer to said bonding layer at least through said one or plurality of throughholes. Finally, by mounting a semiconductor chip on said chip-mounting substrate, the multichip-module fabrication method is completed.