Patents by Inventor Toshiyuki Maenosono
Toshiyuki Maenosono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569089Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.Type: GrantFiled: August 24, 2020Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
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Publication number: 20220059346Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region. having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.Type: ApplicationFiled: August 24, 2020Publication date: February 24, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
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Patent number: 11257744Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.Type: GrantFiled: August 16, 2019Date of Patent: February 22, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
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Publication number: 20190371720Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.Type: ApplicationFiled: August 16, 2019Publication date: December 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
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Patent number: 10418311Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.Type: GrantFiled: March 28, 2017Date of Patent: September 17, 2019Assignee: Micron Technology, Inc.Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
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Publication number: 20180286795Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: Micron Technology, Inc.Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
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Patent number: 7679194Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: GrantFiled: April 10, 2007Date of Patent: March 16, 2010Assignee: Fujitsu AMD Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20070187833Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: April 10, 2007Publication date: August 16, 2007Applicant: Fujitsu Amd Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20050006672Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: August 12, 2004Publication date: January 13, 2005Applicant: Fujitsu AMD Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
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Patent number: 6794248Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: GrantFiled: October 25, 2002Date of Patent: September 21, 2004Assignee: Fujitsu Amd Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20030162354Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: October 25, 2002Publication date: August 28, 2003Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi