Patents by Inventor Toshiyuki Maenosono

Toshiyuki Maenosono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569089
    Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
  • Publication number: 20220059346
    Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region. having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 24, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
  • Patent number: 11257744
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 22, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Publication number: 20190371720
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Patent number: 10418311
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Publication number: 20180286795
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Patent number: 7679194
    Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: March 16, 2010
    Assignee: Fujitsu AMD Semiconductor Limited
    Inventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
  • Publication number: 20070187833
    Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.
    Type: Application
    Filed: April 10, 2007
    Publication date: August 16, 2007
    Applicant: Fujitsu Amd Semiconductor Limited
    Inventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
  • Publication number: 20050006672
    Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 13, 2005
    Applicant: Fujitsu AMD Semiconductor Limited
    Inventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
  • Patent number: 6794248
    Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: September 21, 2004
    Assignee: Fujitsu Amd Semiconductor Limited
    Inventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
  • Publication number: 20030162354
    Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.
    Type: Application
    Filed: October 25, 2002
    Publication date: August 28, 2003
    Applicant: FUJITSU AMD SEMICONDUCTOR LIMITED
    Inventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi