Patents by Inventor Toshiyuki Morishige

Toshiyuki Morishige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899971
    Abstract: An offset detection circuit includes: a comparison unit that generates a first comparison result between an amplifier output and a positive detection threshold value, and a second comparison result between the amplifier output and a negative detection threshold value; a first determination unit that generates a first offset determination result of two values indicating presence or absence of an offset according to a period during which the amplifier output exceeds the positive detection threshold value, based on the first comparison result; a second determination unit that generates a second offset determination result of two values indicating the presence or absence of an offset according to a period during which the amplifier output exceeds the negative detection threshold value, based on the second comparison result; and an output unit that generates a determination output of the offset based on the first and second offset determination results.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shimon Takamiya, Kouichi Yamashita, Toshiyuki Morishige
  • Patent number: 5233496
    Abstract: A low-frequency power amplifier with an integrated BTL output circuit drives a load. The amplifier incorporates a bias circuit for supplying a bias voltage to each circuit composing the amplifier, a control circuit for switching between the normal operation mode and the mode for detecting the load being in an open-circuit condition, a detector circuit for detecting the load being in an open-circuit mode by supplying current to the load and sensing the current flowing through the load, and an output circuit for telling an external circuit of the integrated circuit that the load is in an open-circuit mode. All these circuits are squeezed into a single chip. The control circuit controls the bias circuit and detector circuit. During normal operation, the BTL output circuit is in an operative state, while the detector circuit is in a nonoperative state.
    Type: Grant
    Filed: March 13, 1991
    Date of Patent: August 3, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Morishige
  • Patent number: 5166854
    Abstract: A power supply abnormality detection system of the present invention includes a low-frequency power amplifier circuit equipped with a built-in overvoltage protection circuit for detecting a voltage exceeding, for example, a reference power supply voltage. In accordance with the presence or absence of an overvoltage detected by the overvoltage protection circuit, a detection signal emerges from a detection output terminal provided outside the low-frequency power amplifier circuit. In accordance with that emerging detection signal, a counting circuit counts an overvoltage detection amount as pulses and, when the number of pulses exceeds a predetermined reference number, a power supply line relay section is operated so as to interrupt the supply of that overvoltage and an abnormality alarm device informs the generation of the overvoltage to an outside.
    Type: Grant
    Filed: March 9, 1990
    Date of Patent: November 24, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Morishige