Patents by Inventor Toshiyuki Muta
Toshiyuki Muta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7620138Abstract: A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, this apparatus selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal.Type: GrantFiled: November 29, 2004Date of Patent: November 17, 2009Assignee: Fujitsu LimitedInventor: Toshiyuki Muta
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Publication number: 20060002399Abstract: A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up time and a hold time of the data signal are secured for each bit or for each group of parallel data. Then, this apparatus selects the data of a plurality of bits in the data buffer in chronological order and reads out the selected data as parallel data, in accordance with a second clock signal.Type: ApplicationFiled: November 29, 2004Publication date: January 5, 2006Applicant: FUJITSU LIMITEDInventor: Toshiyuki Muta
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Patent number: 6772297Abstract: To perform a data replace control activated prior to the execution of a cache memory reference instruction so as to reduce the latency when a miss occurs to a cache memory. In a cache replace control of a load store unit, a load store unit controlling device comprises a first queue selection logical circuit 41, a second queue selection logical circuit 42 and a mediating unit 43, wherein the first queue selection logical circuit sequentially selects access instructions to access the cache memory which are stored in queues 31, wherein the second queue selection logical circuit selects unissued access instructions of the access instructions to access the cache memory which are stored in the queues prior to the selections by the first queue selection logical circuit, and wherein the mediating unit mediates between the access instructions selected by the first queue selection logical circuit and the pre-access instructions selected by the second queue selection logical circuit for accessing the cache memory.Type: GrantFiled: March 27, 2001Date of Patent: August 3, 2004Assignee: Fujitsu LimitedInventor: Toshiyuki Muta
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Patent number: 6708294Abstract: A cache memory apparatus includes a primary cache memory using a 4-way set associative method and a secondary cache memory. When a parity error occurs in an entry in the primary cache memory, the way is prohibited from being replaced, and data related to the entry is written back from the primary cache memory to the secondary cache memory. Thereafter, the entry in the primary cache memory is made invalid, and the prohibition on the replacement of the way is released. When the secondary cache memory is accessed, the data written back is moved from the secondary cache memory to the entry into the primary cache memory to set a status before the parity error occurs.Type: GrantFiled: October 26, 2000Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Manabu Nakao, Toshiyuki Muta, Makoto Hataida
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Patent number: 6681294Abstract: A cache control apparatus for an information processing system having a cache memory with a plurality of ways is disclosed, in which the hardware amount is reduced and the delay of the response time is minimized. At the time of cache access, each way is indexed by time division, and when updating the cache, a way to be updated is designated thereby to update the cache tag and the cache data. The data indexed by time division can be judged for a hit each time of indexing or alternatively, the data of all the ways are judged for a hit after being held in a buffer. The data indexed by time division is sent to the reader as response without regard to the way, and when a miss is judged, a cancel signal is sent thereby to minimize the access time delay. Further by predicting the address of a way, the access time can be further improved.Type: GrantFiled: March 29, 2000Date of Patent: January 20, 2004Assignee: Fujitsu LimitedInventors: Shinya Kato, Toshiyuki Muta
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Patent number: 6546501Abstract: A cache memory apparatus includes a primary cache memory using a 4-way set associative method and a secondary cache memory. When a parity error occurs in an entry in the primary cache memory, the way is prohibited from being replaced, and data related to the entry is written back from the primary cache memory to the secondary cache memory. Thereafter, the entry in the primary cache memory is made invalid, and the prohibition on the replacement of the way is released. When the secondary cache memory is accessed, the data written back is moved from the secondary cache memory to the entry into the primary cache memory to set a status before the parity error occurs.Type: GrantFiled: March 20, 2000Date of Patent: April 8, 2003Assignee: Fujitsu LimitedInventors: Makoto Hataida, Manabu Nakao, Toshiyuki Muta
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Patent number: 6442665Abstract: A calculating part performs calculation. A storing part stores data from the calculating part. An address converting part converts an address corresponding to data requested by the calculating part. A first comparing part compares an address from the address converting part and data stored in the storing part. A second comparing part compares the address corresponding to the data requested by the calculating part with an address of said storing part. A selecting part selects the data stored in the storing part to be provided to the calculating part when an address comparison result of the first comparing part is coincidence and also an address comparison result of the second comparing part is coincidence.Type: GrantFiled: January 4, 2001Date of Patent: August 27, 2002Assignee: Fujitsu LimitedInventors: Makoto Hataida, Toshiyuki Muta
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Publication number: 20020040421Abstract: To perform a data replace control activated prior to the execution of a cache memory reference instruction so as to reduce the latency when a miss occurs to a cache memory.Type: ApplicationFiled: March 27, 2001Publication date: April 4, 2002Applicant: FUJITSU LIMITED KAWASAKI, JAPANInventor: Toshiyuki Muta
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Publication number: 20010056517Abstract: A calculating part performs calculation. A storing part stores data from the calculating part. An address converting part converts an address corresponding to data requested by the calculating part. A first comparing part compares an address from the address converting part and data stored in the storing part. A second comparing part compares the address corresponding to the data requested by the calculating part with an address of said storing part. A selecting part selects the data stored in the storing part to be provided to the calculating part when an address comparison result of the first comparing part is coincidence and also an address comparison result of the second comparing part is coincidence.Type: ApplicationFiled: January 4, 2001Publication date: December 27, 2001Inventors: Makoto Hataida, Toshiyuki Muta
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Patent number: 6092173Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.Type: GrantFiled: March 26, 1997Date of Patent: July 18, 2000Assignees: Fujitsu Limited, PFU LimitedInventors: Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Yozo Nakayama, Jun Sakurai, Toshiyuki Muta, Takayuki Shimamura
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Patent number: 6038674Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.Type: GrantFiled: July 13, 1999Date of Patent: March 14, 2000Assignees: Fujitsu Limited, PFU LimitedInventors: Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura
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Patent number: 6029219Abstract: A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitration between the requests, a circuit updating the value in the register among the N values in a predetermined order synchronously with the arbitration, and a circuit updating the value in the register among the N values in the predetermined order at regular intervals that are asynchronous with the arbitration. At the regular intervals that are asynchronous with the arbitration, a jump is made in the predetermined updating order of the values to be set in the register. Accordingly, even if live-lock occurs, it will be solved when such a jump is made to make the number of priority patterns disagree with the number of requests issued in a loop.Type: GrantFiled: February 25, 1998Date of Patent: February 22, 2000Assignee: Fujitsu LimitedInventors: Masatoshi Michizono, Toshiyuki Muta, Koichi Odahara, Yasutomo Sakurai, Shinya Katoh
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Patent number: 5890217Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.Type: GrantFiled: February 7, 1996Date of Patent: March 30, 1999Assignees: Fujitsu Limited, PFU LimitedInventors: Akira Kabemoto, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura, Hirohide Sugahara, Junji Nishioka, Takatsugu Sasaki, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Hiroaki Ishihata, Takeshi Horie, Toshiyuki Shimizu