Patents by Inventor Toshiyuki Nakaie

Toshiyuki Nakaie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8829972
    Abstract: An integral value measuring circuit includes an operational amplifier and a capacitor connected between input and output sides thereof, an electric potential of an output terminal where a predetermined resistance element connected to an output side of the operational amplifier is being zero, positive and negative DC voltage generating circuits which comprise positive and negative power sources, respectively, at the output side of the operational amplifier, the positive and negative DC voltage generating circuits and being connected to positive and negative power terminals, respectively, of the operational amplifier through switches, and a connection line between the negative power terminal and one switch and a connection line between the positive power terminal and another switch being connected to the positive and negative power terminals, respectively, of the operational amplifier through cross resistance elements having resistance values negligible compared to a leakage resistance value of the switches.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 9, 2014
    Assignee: Hanwa Electronic Ind. Co., Ltd.
    Inventors: Toshiyuki Nakaie, Joji Kayano
  • Patent number: 8410791
    Abstract: The application methods in the related art cannot apply a sufficient voltage with a rectangular wave having a short rise time to an electronic circuit. Furthermore, electrostatic discharge test can apply a sufficient voltage but can only apply an oscillating waveform. A TLP generator is used as a rectangular wave generator. The sum of an injection resistance and a matching resistance is set so as to match the characteristic impedance of a transmission line for transmitting a rectangular wave to a test target. A capacitor is connected to a return line of the applied rectangular wave. With this configuration, stable application can be achieved. An error observation function of an electronic circuit gradually increases a peak value of the rectangular wave and determines the immunity based on an application voltage to cause an error for the first time.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 2, 2013
    Assignees: NEC Corporation, Renesas Electronics Corporation, Hanwa Electronic Ind. Co., Ltd.
    Inventors: Tsuneo Tsukagoshi, Takeshi Watanabe, Toshiyuki Nakaie, Nobuchika Matsui
  • Publication number: 20130009628
    Abstract: An integral value measuring circuit includes an operational amplifier and a capacitor connected between input and output sides thereof, an electric potential of an output terminal where a predetermined resistance element connected to an output side of the operational amplifier is being zero, positive and negative DC voltage generating circuits which comprise positive and negative power sources, respectively, at the output side of the operational amplifier, the positive and negative DC voltage generating circuits and being connected to positive and negative power terminals, respectively, of the operational amplifier through switches, and a connection line between the negative power terminal and one switch and a connection line between the positive power terminal and another switch being connected to the positive and negative power terminals, respectively, of the operational amplifier through cross resistance elements having resistance values negligible compared to a leakage resistance value of the switches.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 10, 2013
    Applicant: HANWA ELECTRONIC IND. CO., LTD.
    Inventors: Toshiyuki Nakaie, Joji Kayano
  • Patent number: 8267728
    Abstract: A receptacle includes a signal terminal, a ground terminal, and a signal terminal. A second portion of the ground terminal is distanced from a first portion of the signal terminal in an extension direction. A third portion of the signal terminal is distanced from the first portion of the signal terminal in the extension direction.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: September 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Nakaie, Hirotsugu Fusayasu, Shouichi Mimura, Masafumi Kumoi, Ryo Matsubara
  • Patent number: 8162671
    Abstract: A receptacle structure includes a housing structure, a terminal insulating board, a first terminal and a second terminal. The housing structure is configured to be mounted on a printed wiring board and to accommodate a plug. The terminal insulating board includes a top face and a bottom face that is opposite to the top face. The terminal insulating board is disposed inside the housing structure with the bottom face facing towards the printed wiring board. The first terminal is connected to the printed wiring board via the first rear connection part and to the terminal insulating board. The second terminal is connected to the printed wiring board via the first front connection part and to the terminal insulating board. The first front connection part has a width narrower than the first rear connection part and is connected to the printed wiring board away from the first rear connection part.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryou Matsubara, Shouichi Mimura, Hirotsugu Fusayasu, Masafumi Kumoi, Toshiyuki Nakaie
  • Patent number: 8072778
    Abstract: A plasma display device capable of reducing an electromagnetic interference wave due to a driving current flowing in a plasma display panel is provided. The plasma display device includes a plasma display panel having electrodes that are parallel to each other, a driver circuit board for applying a voltage to the electrodes, a chassis conductor holding the plasma display panel and to which a ground of the driver circuit board is connected, and a first additional conductor plate provided to the chassis conductor via an insulating layer and to which grounds of at least one circuit board in circuit boards other than the driver circuit board are attached.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: December 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Kunimoto, Hirotsugu Fusayasu, Shouichi Mimura, Kei Ichikawa, Masafumi Kumoi, Ryo Matsubara, Masato Tobinaga, Toshiyuki Nakaie
  • Publication number: 20110256739
    Abstract: A receptacle includes a signal terminal, a ground terminal, and a signal terminal. A second portion of the ground terminal is distanced from a first portion of the signal terminal in an extension direction. A third portion of the signal terminal is distanced from the first portion of the signal terminal in the extension direction.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 20, 2011
    Applicant: Panasonic Corporation
    Inventors: Toshiyuki Nakaie, Hirotsugu Fusayasu, Shouichi Mimura, Masafumi Kumoi, Ryo Matsubara
  • Publication number: 20110201214
    Abstract: A receptacle structure includes a housing structure, a terminal insulating board, a first terminal and a second terminal. The housing structure is configured to be mounted on a printed wiring board and to accommodate a plug. The terminal insulating board includes a top face and a bottom face that is opposite to the top face. The terminal insulating board is disposed inside the housing structure with the bottom face facing towards the printed wiring board. The first terminal is connected to the printed wiring board via the first rear connection part and to the terminal insulating board. The second terminal is connected to the printed wiring board via the first front connection part and to the terminal insulating board. The first front connection part has a width narrower than the first rear connection part and is connected to the printed wiring board away from the first rear connection part.
    Type: Application
    Filed: July 16, 2010
    Publication date: August 18, 2011
    Applicant: Panasonic Corporation
    Inventors: Ryou MATSUBARA, Shouichi Mimura, Hirotsugu Fusayasu, Masafumi Kumoi, Toshiyuki Nakaie
  • Publication number: 20110201215
    Abstract: In a receptacle, a ground terminal includes a bottom face connection portion connected to a bottom face of a terminal insulating board and a forward connection portion that is distanced from an opening. A signal terminal includes a top face connection portion connected to a top face on the opposite side of the bottom face connection portion and a rearward connection portion that is provided closer to the opening than the forward connection portion.
    Type: Application
    Filed: April 8, 2010
    Publication date: August 18, 2011
    Applicant: Panasonic Corporation
    Inventors: Ryo Matsubara, Shouichi Mimura, Hirotsugu Fusayasu, Masafumi Kumoi, Toshiyuki Nakaie
  • Publication number: 20100090710
    Abstract: The application methods in the related art cannot apply a sufficient voltage with a rectangular wave having a short rise time to an electronic circuit. Furthermore, electrostatic discharge test can apply a sufficient voltage but can only apply an oscillating waveform. A TLP generator is used as a rectangular wave generator. The sum of an injection resistance and a matching resistance is set so as to match the characteristic impedance of a transmission line for transmitting a rectangular wave to a test target. A capacitor is connected to a return line of the applied rectangular wave. With this configuration, stable application can be achieved. An error observation function of an electronic circuit gradually increases a peak value of the rectangular wave and determines the immunity based on an application voltage to cause an error for the first time.
    Type: Application
    Filed: March 6, 2008
    Publication date: April 15, 2010
    Applicants: NEC Corporation, NEC Electronics Corporation, Hanwa Electronic Ind. Co., Ltd.
    Inventors: Tsuneo Tsukagoshi, Takeshi Watanabe, Toshiyuki Nakaie, Nobuchika Matsui
  • Patent number: 7609076
    Abstract: A method of quickly measuring a characteristic impedance of an ESD protecting circuit by applying a discharge voltage to the ESD protecting circuit, includes the steps of measuring a variation in discharge voltage applied to and a variation in discharge current caused to flow through the ESD protecting circuit with time; simultaneously detecting a state when both the discharge voltage and discharge current corresponding to each other are attenuated, after both the discharge voltage and discharge current sequentially rise to arrive individually to respective peak values based on an input to or an output from a computer; and taking a ratio of the variation of discharge voltage to the variation of discharge current during the attenuation as an impedance value when the ratio is nearly constant as well as an apparatus for realizing the same.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: October 27, 2009
    Assignee: Hanwa Electronic Ind. Co., Ltd.
    Inventors: Toshiyuki Nakaie, Masanori Sawada, Taizo Shintani, Natarajan Mahadeva Iyer, David Eric Tremouilles
  • Publication number: 20090251390
    Abstract: A plasma display device including a plasma display panel having electrodes through which a driving current flows; a chassis conductor holding the plasma display panel and provided with a return circuit of the driving current; a conductive case enclosing the plasma display panel and the chassis conductor; and a binding portion for binding the chassis conductor and the conductive case to each other and having a connection state different depending upon a frequency of flowing current. The binding portion has a connection state in which an amount of flowing current is less than a half of that in a short-circuited state and a connection state in which the amount is not less than a half of that in a short-circuited state.
    Type: Application
    Filed: March 16, 2009
    Publication date: October 8, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Masafumi Kumoi, Hirotsugu Fusayasu, Hiroshi Kunimoto, Kei Ichikawa, Shouichi Mimura, Ryo Matsubara, Masato Tobinaga, Toshiyuki Nakaie
  • Publication number: 20090237907
    Abstract: A plasma display device capable of reducing an electromagnetic interference wave due to a driving current flowing in a plasma display panel is provided. The plasma display device includes a plasma display panel having electrodes that are parallel to each other, a driver circuit board for applying a voltage to the electrodes, a chassis conductor holding the plasma display panel and to which a ground of the driver circuit board is connected, and a first additional conductor plate provided to the chassis conductor via an insulating layer and to which grounds of at least one circuit board in circuit boards other than the driver circuit board are attached.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 24, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Kunimoto, Hirotsugu Fusayasu, Shouichi Mimura, Kei Ichikawa, Masafumi Kumoi, Ryo Matsubara, Masato Tobinaga, Toshiyuki Nakaie
  • Publication number: 20090231238
    Abstract: A plasma display device includes a plasma display module having a plasma display panel provided with a plurality of parallel electrodes, a circuit board for applying a voltage to the electrodes, and a chassis conductor configured to hold the plasma display panel and to which a ground of a circuit board is coupled, and further includes a cylindrical conductor portion configured to surround the plasma display module.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 17, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Hirotsugu Fusayasu, Shouichi Mimura, Hiroshi Kunimoto, Kei Ichikawa, Masafumi Kumoi, Ryo Matsubara, Masato Tobinaga, Toshiyuki Nakaie
  • Publication number: 20080004820
    Abstract: A method of quickly measuring a characteristic impedance of an ESD protecting circuit by applying a discharge voltage to the ESD protecting circuit, includes the steps of measuring a variation in discharge voltage applied to and a variation in discharge current caused to flow through the ESD protecting circuit with time, grasping a state until both the discharge voltage and discharge current corresponding to each other whenever a predetermined common time elapses comes to an attenuation process after both the discharge voltage and discharge current sequentially rise to come individually to respective peak values based on an input to or an output from a computer; and taking a ratio of the variation of discharge voltage to the variation of discharge current in the attenuation process as an impedance value when the ratio is nearly constant as well as an apparatus for realizing the same.
    Type: Application
    Filed: May 17, 2007
    Publication date: January 3, 2008
    Applicant: HANWA ELECTRONIC IND. CO., LTD.
    Inventors: Toshiyuki NAKAIE, Masanori SAWADA, Taizo SHINTANI, Natarajan Mahadeva IYER, David Eric TREMOUILLES
  • Patent number: 5740007
    Abstract: A CDM simulator for use with an integrated circuit having a terminal and for use with a grounding conductor, includes a cylindrical conductor, and a mercury lead switch contained in the cylindrical conductor, the mercury lead switch having a first end connected to the cylindrical conductor and a second end for connection to the terminal of the integrated circuit, and the mercury lead switch having a first length, the cylindrical conductor having an end closer to the terminal of the integrated circuit for connection to the grounding conductor in order to release electric charge from the integrated circuit to the grounding conductor, and the cylindrical conductor having a second length longer than the first length of the mercury lead switch.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: April 14, 1998
    Assignee: Hanwa Electronic Ind. Co., Ltd.
    Inventors: Toshiyuki Nakaie, Akira Yoshino, Shin Yoshida, Kenichi Sengo
  • Patent number: 4677375
    Abstract: An apparatus for testing plug-in type integrated circuits by applying a potential across their input and output terminals, utilizing a socket board with a plurality of sockets bored therein to receive respective input and output terminals of an integrated circuit. A pair of first and second groups of fixed contacts are located in the socket board, arranged in two concentric circles enclosing the sockets. Each fixed contact in each group is individually connected to one of the sockets through a conductor. A pair of coaxial first and second moving contact pins is rotatably disposed below the socket board. The first contact pin rotates to follow the first circle while sequentially contacting the contacts of the first group. The second contact pin follows the second circle, making sequential contact with the fixed contacts of the second group.
    Type: Grant
    Filed: June 14, 1985
    Date of Patent: June 30, 1987
    Assignee: Hanwa Electronic Co., Ltd.
    Inventors: Toshiyuki Nakaie, Akira Yoshino