Abstract: Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.

Abstract: Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.

Abstract: Delay circuits apply a delay to set and reset pulses, respectively. An RS flip-flop is set according to the set pulse that has passed through the set delay circuit, and is reset according to the reset pulse received from the reset delay circuit. A demultiplexer receives the reset pulse that has passed through the reset delay circuit. In a first state, the demultiplexer outputs the reset pulse to the reset terminal of the RS flip-flop. In a second state, the demultiplexer outputs the reset pulse signal to the reset delay circuit again, thereby forming a closed loop. A loop control unit counts the number of times a pulse is passed through the loop. When the number of passes through the closed loop reaches a predetermined value, the demultiplexer is set to the first state.

Abstract: A test apparatus is configured such that two adjacent channels form a pair. Timing comparators determine the level of first output data fed from a DUT, respectively, timed in accordance with strobe signals, respectively. Clock envelope extractors extract envelopes of a clock, respectively. A clock recovery circuit recovers a strobe signal. A first main latch latches an output from the first timing comparator, timed by the first strobe signal. A first sub-latch latches the envelope of the clock, timed by the first strobe signal. An output from the sub-latch is supplied to a second main latch of the second channel. A signal dependent on the strobe signal is assigned an adjustable delay by a first delay circuit and is supplied to a clock terminal of the second main latch.

Abstract: A test apparatus is configured such that two adjacent channels form a pair. Timing comparators determine the level of first output data fed from a DUT, respectively, timed in accordance with strobe signals, respectively. Clock envelope extractors extract envelopes of a clock, respectively. A clock recovery circuit recovers a strobe signal. A first main latch latches an output from the first timing comparator, timed by the first strobe signal. A first sub-latch latches the envelope of the clock, timed by the first strobe signal. An output from the sub-latch is supplied to a second main latch of the second channel. A signal dependent on the strobe signal is assigned an adjustable delay by a first delay circuit and is supplied to a clock terminal of the second main latch.

Abstract: After chemical nickel plating has been applied onto a rotor-side surface 10 of a caliper 5a made of aluminum alloy and an opposite surface 11 disposed in an opposite side of the rotor-side surface, nickel-tungsten alloy plating is applied onto these both surfaces 10, 11. Then, gold plating is applied onto only the rotor-side surface 10. As a result, a reflectance to incident light on the rotor-side surface 10 is made higher than a reflectance to incident light on the opposite surface 11.

Abstract: There is provided a timing generator for generating a timing signal based on a given reference clock, having a delaying circuit section for outputting each pulse of the reference clock by delaying by a value of delay given per each of the pulse and a pulse selecting and outputting section for passing and outputting only pulses to be outputted as the timing signal among the pulses outputted out of the delaying circuit section.

Abstract: A signal output circuit for outputting an output signal in accordance with a predetermined system timing is provided. The signal output circuit includes a shift register that delays an input signal in accordance with the system timing, a flip-flop that receives the input signal delayed by the shift register in response to a clock signal supplied thereto, and outputs the input signal as the output signal, and an initializing section that measures a delay amount achieved by the shift register and judges whether the measured delay amount is in accordance with the system timing.

Abstract: After chemical nickel plating has been applied onto a rotor-side surface 10 of a caliper 5a made of aluminum alloy and an opposite surface 11 disposed in an opposite side of the rotor-side surface, nickel-tungsten alloy plating is applied onto these both surfaces 10, 11. Then, gold plating is applied onto only the rotor-side surface 10. As a result, a reflectance to incident light on the rotor-side surface 10 is made higher than a reflectance to incident light on the opposite surface 11.

Abstract: Intends to provide semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal to be extracted from data or a time required in adjustment. It includes a timing comparator 154 for receiving data outputted from a DUT 200; a clock generating circuit 120 for generating a clock signal synchronized with data outputted from the DUT 200; an absolute amount of delay calculating unit for calculating a signal propagating time corresponding to a difference between a first signal line from the DUT 200 to the timing comparator 154 and a second signal line to the clock generating circuit 120 as an absolute amount of delay; and an amount of delay setting unit for setting the amount of delay under a period of the clock signal according to a frequency or a period of the clock signal generated by the clock generating circuit 120 and ordering adjustment of the clock signal generating timing by the clock generating circuit 120.

Abstract: A signal output circuit for outputting an output signal in accordance with a predetermined system timing is provided. The signal output circuit includes a shift register that delays an input signal in accordance with the system timing, a flip-flop that receives the input signal delayed by the shift register in response to a clock signal supplied thereto, and outputs the input signal as the output signal, and an initializing section that measures a delay amount achieved by the shift register and judges whether the measured delay amount is in accordance with the system timing.

Abstract: Intends to provide semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal to be extracted from data or a time required in adjustment. It includes a timing comparator 154 for receiving data outputted from a DUT 200; a clock generating circuit 120 for generating a clock signal synchronized with data outputted from the DUT 200; an absolute amount of delay calculating unit for calculating a signal propagating time corresponding to a difference between a first signal line from the DUT 200 to the timing comparator 154 and a second signal line to the clock generating circuit 120 as an absolute amount of delay; and an amount of delay setting unit for setting the amount of delay under a period of the clock signal according to a frequency or a period of the clock signal generated by the clock generating circuit 120 and ordering adjustment of the clock signal generating timing by the clock generating circuit 120.

Abstract: A waveform formatter according to the present invention includes a first delay circuit for delaying a set signal to control the timing of a first change point of a test signal, a second delay circuit for delaying a reset signal to control the timing of a second change point of the test signal changed by the set signal which the first delay circuit delays, a third delay circuit for delaying a set signal to control the timing of a third change point of the test signal, a fourth delay circuit for delaying a reset signal to control the timing of a fourth change point of the test signal changed by the set signal which is delayed by the third delay circuit, a fifth delay circuit for delaying a set signal to control the timing of a first change point of an enable signal of the driver, a sixth delay circuit for delaying a reset signal to control the timing of a second change point of an enable signal with regard to the driver during a predetermined cycle of a cycle reference signal.

Abstract: There is provided a timing generator for generating a timing signal based on a given reference clock, having a delaying circuit section for outputting each pulse of the reference clock by delaying by a value of delay given per each of the pulse and a pulse selecting and outputting section for passing and outputting only pulses to be outputted as the timing signal among the pulses outputted out of the delaying circuit section.

Abstract: A waveform formatter according to the present invention includes a first delay circuit for delaying a set signal to control the timing of a first change point of a test signal, a second delay circuit for delaying a reset signal to control the timing of a second change point of the test signal changed by the set signal which the first delay circuit delays, a third delay circuit for delaying a set signal to control the timing of a third change point of the test signal, a fourth delay circuit for delaying a reset signal to control the timing of a fourth change point of the test signal changed by the set signal which is delayed by the third delay circuit, a fifth delay circuit for delaying a set signal to control the timing of a first change point of an enable signal of the driver, a sixth delay circuit for delaying a reset signal to control the timing of a second change point of an enable signal with regard to the driver during a predetermined cycle of a cycle reference signal.

Abstract: An IC tester is provided which is capable of performing a high speed test of an IC under test without using a plurality of pin units for one pin of the IC under test. For each of pins of an IC under test are provided first and second two pattern generators first and second waveform shaping devices having waveform memories and respectively, first and second logical comparators and first and second failure analysis memories. Odd addresses of the first waveform memory are accessed by the first pattern generator, even addresses of the second waveform memory are accessed by the second pattern generator, and waveform data from these two waveform shaping devices are multiplexed for half of the period of a test pattern signal of the normal speed to set and reset first and scond set/reset flip-flops SRFF1 and SRFF2. As a result, a test pattern signal of high speed of twice the normal speed is produced and a test of an IC under test is implemented at high speed of twice the normal speed.

Abstract: A calibration data transmission apparatus and method for a semiconductor test equipment is disclosed which is capable of decreasing the capacity of a memory for storing the calibration data and also reducing the time for transmitting the calibration data. The calibration data transmission apparatus includes a pin mode data memory which stores different types of calibration mode data for each test pin, a calibration file memory which stores calibration data each of which corresponds to each test pin and the calibration mode data, and a calibration flag circuit which detects a coincidence between the calibration data to be transmitted and the previous calibration data.

Abstract: A waveform formatter for use in testing a semiconductor device is capable of reducing a total size of circuit configuration. The waveform formatter includes a plurality of clock generators in which at low-speed operation, clocks are used to generate waveforms and control signals of drivers, while at high-speed operation, all clocks are used to generate waveforms for drivers. The waveform formatter further includes a parallel-serial converter for converting parallel signals to a serial signal, a data selector for selecting the parallel signals or the serial signal, and a waveform combining circuit for accepting output signals of the clock generators through a format control unit and for generating waveforms and control signals for the drivers using the clocks from the clock generators.

Abstract: A dust-proof boot comprising an internal engaging ring extended from one end of an expansible bellows portion and an external engaging ring provided upwardly thereof and capable of being spread is provided at an extended base of the internal engaging ring with an air flow port for guiding pressure from the inside of the bellows portion into the internal engaging ring. In mounting the dust-proof boot on a support provided with a guide hole, the internal engaging ring of the dust-proof boot is fitted into an internal groove of the support, after which compressed air is supplied from the interior of the bellows whereby the compressed air spreads the external engaging ring via the air flow port and the external engaging ring is fitted into an external groove.