Abstract: A solid state imaging device with (a) an amplifier transistor; an input node for the amplifier transistor; or both the amplifier transistor and the input node for the amplifier transistor; (b) a plurality of photoelectric conversion elements; (c) a like plurality of storage transistors, each configured to act as a photo-charge storage node to store charges generated by a respective photoelectric conversion element; and (d) a like plurality of transfer transistors, each configured to transfer charges from a respective photoelectric conversion element to a common output, the common output being either the amplifier transistor or the input node for the amplifier transistor.

Abstract: A solid-state imaging device includes: a pixel circuit including a photoelectric conversion device and an amp device that outputs electric charges, which are photoelectrically converted by the photoelectric conversion device, through electric potential modulation of an output signal line; and a reading section including an AD (analog digital) conversion circuit that compares an output level of the signal line with a reference signal which changes with a regular slope and digitalizes an output signal on the basis of a timing at which a previously-defined relationship is satisfied between the output signal and the reference signal.

Abstract: An imaging device includes: a pixel array section having an array of pixels, each of which has a photoelectric converting device and outputs an electric signal according to an input photon; a sense circuit section having a plurality of sensor circuits each of which makes binary decision on whether there is a photon input to a pixel in a predetermined period upon reception of the electric signal therefrom; and a decision result IC section which integrates decision results from the sense circuits, pixel by pixel or for each group of pixels, multiple times to generate imaged data with a gradation, the decision result IC section including a count circuit which performs a count process to integrate the decision results from the sense circuits, and a memory for storing a counting result for each pixel from the count circuit, the sense circuits sharing the count circuit for integrating the decision results.

Abstract: A pixel circuit has first, second, and third field effect transistors integrated and connected in series from a photoelectric conversion element to a side of an amplifier circuit. The first and second field effect transistors have gate electrodes to be simultaneously collectively driven. A threshold voltage of the first field effect transistor is set to be higher than that of the second field effect transistor. As the gate electrodes are driven step by step, electrons generated by the photoelectric conversion element and transferred via the first field effect transistor are accumulated in a channel region of the second field effect transistor. The electrons accumulated in the channel region are transferred to an input of the amplifier circuit via the third field effect transistor.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Abstract: An image sensor includes a plurality of pixels, a plurality of sense circuits, and a count circuit. Each sense circuit is configured to read out electrical signals from at least one pixel associated with the sense circuit in order to generate data representing whether or not photons have been received by the sense circuit. The count circuit is in communication with a sense circuit selected from the plurality of sense circuits. The count circuit is configured to provide integration results for the pixels associated with the sense circuits based on the data received from the sense circuits.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Abstract: An image sensor includes a plurality of pixels, a plurality of sense circuits, and a count circuit. Each sense circuit is configured to read out electrical signals from at least one pixel associated with the sense circuit in order to generate data representing whether or not photons have been received by the sense circuit. The count circuit is in communication with a sense circuit selected from the plurality of sense circuits. The count circuit is configured to provide integration results for the pixels associated with the sense circuits based on the data received from the sense circuits.

Abstract: An imaging device includes: a pixel array section having an array of pixels each of which has a photoelectric converting device and outputs an electric signal according to an input photon; a sense circuit section having a plurality of sensor circuits each of which makes binary decision on whether there is a photon input to a pixel in a predetermined period upon reception of the electric signal therefrom; and a decision result IC section which integrates decision results from the sense circuits, pixel by pixel or for each group of pixels, multiple times to generate imaged data with a gradation, the decision result IC section including a count circuit which performs a count process to integrate the decision results from the sense circuits, and a memory for storing a counting result for each pixel from the count circuit, the plurality of sense circuits sharing the count circuit for integrating the decision results.

Abstract: A pixel circuit includes: a photoelectric conversion device; a source-follower circuit; a transfer transistor that transfers charge generated in the photoelectric conversion device to an input node of the source-follower circuit; and a readout system that reads out a signal in response to the generated charge through the source-follower circuit, wherein the readout system floats the input node of the source-follower circuit and turns on the transfer transistor to transfer the signal charge to the input node, includes a function of turning off the transfer transistor, sensing an output node potential of the source-follower circuit, and reading out an output signal, and further includes an output modulation degree control function unit that temporarily reduces an output modulation degree of the source-follower circuit when the transfer transistor is turned on.

Abstract: An imaging element includes: a pixel section in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix; a signal line to which a signal read from the pixels is transmitted; a holding section for holding the read signal during a holding period; a processing section for performing signal processing on the read signal after being held by the holding section; and a control section for controlling supply of the read signal to the holding section. The control section supplies the read signal to the holding section to cause it to hold the read signal during the holding period, and stops supplying the read signal to the holding section to cause the processing section to perform the signal processing on the read signal and to cause a signal to be read from the pixels and output to the signal line after the holding.

Abstract: A storage device, enabling elimination of redundant write operations of non-selected data and enabling optimization of arrangement of pages to a state efficient for rewriting, having two flash memories which can be accessed in parallel, a page register for acquiring data in parallel from the flash memories and temporarily storing the same, and a control circuit having a built-in RAM in which is constructed an address conversion table for managing correspondence between logical addresses and physical addresses in units of data stored in parallel in the page register, wherein data is rewritten by updating of the address conversion table and additional writing into a storage medium.

Abstract: An imaging device includes: plural pixel blocks with a predetermined number of pixel circuits of respective plural blocks set as one unit, the plural blocks being obtained by dividing a pixel area formed by arraying plural pixel circuits, which convert incident light into charges according to photoelectric conversion, in a matrix shape; and a selection control unit that selects desired ones of the pixel blocks and collectively executes reset control for discharging charges accumulated by the respective pixel circuits in the selected pixel blocks, wherein the selection control unit changes timing for executing the reset control for each of the selected pixel blocks and allocates different charge accumulating times to the pixel circuits.

Abstract: An imaging device includes: a pixel array section functioning as a light receiving section which includes photoelectric conversion devices and in which a plurality of pixels, which output electric signals when photons are incident, are disposed in an array; a sensing circuit section in which a plurality of sensing circuits, which receive the electric signals from the pixels and perform binary determination regarding whether or not there is an incidence of photons on the pixels in a predetermined period, are arrayed; and a determination result integration circuit section having a function of integrating a plurality of determination results of the sensing circuits for the respective pixels or for each pixel group, wherein the determination result integration circuit section derives the amount of photon incidence on the light receiving section by performing photon counting for integrating the plurality of determination results in the plurality of pixels.

Abstract: A storage device that includes: an address table; a cache memory; a flash memory device that is a storage medium for user data; and a control circuit that is in charge of access management for the flash memory device. In the storage device, the control circuit makes access to the user data on the flash memory device via an address table, in the address table, with an index of an address value generated from an initial logical address, location information is acquired for the user data on the flash memory device corresponding to the index, and the address table is segmented in its entirety into a plurality of small address tables for every area of the index, and the small address tables that are segmentation results are stored in the flash memory device, read as required when the user data is accessed, and expanded on the cache memory with entries of the small address tables.

Abstract: A solid-state imaging device includes: a pixel circuit including a photoelectric conversion device and an amp device that outputs electric charges, which are photoelectrically converted by the photoelectric conversion device, through electric potential modulation of an output signal line; and a reading section including an AD (analog digital) conversion circuit that compares an output level of the signal line with a reference signal which changes with a regular slope and digitalizes an output signal on the basis of a timing at which a previously-defined relationship is satisfied between the output signal and the reference signal.

Abstract: A pixel circuit has first, second, and third field effect transistors integrated and connected in series from a photoelectric conversion element to a side of an amplifier circuit. The first and second field effect transistors have gate electrodes to be simultaneously collectively driven. A threshold voltage of the first field effect transistor is set to be higher than that of the second field effect transistor. As the gate electrodes are driven step by step, electrons generated by the photoelectric conversion element and transferred via the first field effect transistor are accumulated in a channel region of the second field effect transistor. The electrons accumulated in the channel region are transferred to an input of the amplifier circuit via the third field effect transistor.