Abstract: A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB1), a second gate interconnection portion (GHB2), and a third gate interconnection portion (GHB3). The first gate interconnection portion (GHB1) is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region (PER). The second gate interconnection portion (GHB2) is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion (GHB1) toward the power supply interconnection, and extends across a boundary between the element formation region (PER) and an element isolation insulating film (EB), which is in parallel to an X axis direction. The third gate interconnection portion (GHB3) further extends in parallel to the Y-axis direction from the second gate interconnection portion (GHB2) toward the power supply interconnection.

Abstract: A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.

Abstract: A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.

Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

Abstract: A conductive film forming a capacitor lower electrode has portions extending perpendicularly to the main surface of a semiconductor substrate and a portion extending in parallel with the main surface of the semiconductor substrate. An insulator film forming a capacitor dielectric film is provided along the surface of a recess portion defined by the conductive film. Another conductive film forming a capacitor upper electrode is embedded in a recess portion of the insulator film. The conductive film and a wiring layer are formed on the same layer, so that the wiring layer functions as a dummy pattern of a capacitor having the conductive films. Consequently, a semiconductor device having a capacitor capable of increasing the electrostatic capacitance and reducing the quantity of the material forming the dummy pattern without occupying a large area in the direction parallel to the main surface of the semiconductor substrate is obtained.

Abstract: It is an object to provide a semiconductor device in which a structure of a capacitor is simplified. Any electrical connection of a capacitor (CP10) and source—drain regions (11) and (13) is carried out by a contact plug (101) inserted in the capacitor (CP10) and reaching the source—drain regions (11) and (13). The capacitor (CP10) has a capacitor upper electrode (103) provided to be embedded in an upper main surface of an interlayer insulating film (3) and a capacitor dielectric film (102) provided to cover a side surface and a lower surface of the capacitor upper electrode (103). Moreover, the capacitor dielectric film (102) is also provided to cover a side surface of the contact plug (101) formed to penetrate through the capacitor upper electrode (103), and a portion of the contact plug (101) which is covered with the capacitor dielectric film (102) functions as the capacitor lower electrode (101).

Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

Abstract: It is an object to provide a semiconductor device in which a structure of a capacitor is simplified. Any electrical connection of a capacitor (CP10) and source-drain regions (11) and (13) is carried out by a contact plug (101) inserted in the capacitor (CP10) and reaching the source-drain regions (11) and (13). The capacitor (CP10) has a capacitor upper electrode (103) provided to be embedded in an upper main surface of an interlayer insulating film (3) and a capacitor dielectric film (102) provided to cover a side surface and a lower surface of the capacitor upper electrode (103). Moreover, the capacitor dielectric film (102) is also provided to cover a side surface of the contact plug (101) formed to penetrate through the capacitor upper electrode (103), and a portion of the contact plug (101) which is covered with the capacitor dielectric film (102) functions as the capacitor lower electrode (101).

Abstract: A method of producing a semiconductor device having an SOI transistor and a multi-layer wiring, including: preparing a silicon substrate having a front face and a back face; forming an inter-layer insulation layer on the front face of the silicon substrate; forming a multi-layer wiring in the inter-layer insulation layer; fixing a substrate on the inter-layer insulation layer; thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and forming a channel layer and a gate electrode on a back of the channel layer in the SOI layer, and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.

Abstract: A conductive film forming a capacitor lower electrode has portions extending perpendicularly to the main surface of a semiconductor substrate and a portion extending in parallel with the main surface of the semiconductor substrate. An insulator film forming a capacitor dielectric film is provided along the surface of a recess portion defined by the conductive film. Another conductive film forming a capacitor upper electrode is embedded in a recess portion of the insulator film. The conductive film and a wiring layer are formed on the same layer, so that the wiring layer functions as a dummy pattern of a capacitor having the conductive films. Consequently, a semiconductor device having a capacitor capable of increasing the electrostatic capacitance and reducing the quantity of the material forming the dummy pattern without occupying a large area in the direction parallel to the main surface of the semiconductor substrate is obtained.

Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

Abstract: A method of producing a semiconductor device having an SOI transistor and a multi-layer wiring, including: preparing a silicon substrate having a front face and a back face; forming an inter-layer insulation layer on the front face of the silicon substrate; forming a multi-layer wiring in the inter-layer insulation layer; fixing a substrate on the inter-layer insulation layer; thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and forming a channel layer and a gate electrode on a back of the channel layer in the SOI layer, and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.

Abstract: A semiconductor device having copper wiring and capable of reliably preventing copper atoms from diffusing into a memory storage region even in a slight amount is obtained. This semiconductor device includes on a semiconductor substrate a memory cell portion and a wiring portion including copper wires, and includes in a region surrounding the memory cell portion a copper-diffusion preventing film for blocking diffusion of copper atoms from the wiring portion.

Abstract: A semiconductor device having copper wiring and capable of reliably preventing copper atoms from diffusing into a memory storage region even in a slight amount is obtained. This semiconductor device includes on a semiconductor substrate a memory cell portion and a wiring portion including copper wires, and includes in a region surrounding the memory cell portion a copper-diffusion preventing film for blocking diffusion of copper atoms from the wiring portion.

Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

Abstract: Lower wiring lines of a semiconductor memory are covered with a SiN film, and a SiO2 interlayer insulating film is formed over the SiN film. When forming a contact hole, an opening is formed first in the SiO2 interlayer insulating film by anisotropic etching, and then a portion of the SiN film in the opening is removed by isotropic etching. Residues of oxide film, if any, are removed by anisotropic etching to complete a contact hole reaching the semiconductor substrate. Over-etching of the semiconductor substrate is prevented in forming the contact hole, and the contact does not penetrate into a semiconductor substrate.

Abstract: In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

Abstract: A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

Abstract: A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

Abstract: An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.