Abstract: A field effect transistor of the present invention has in a base layer (33) a difference in levels constituted by an upper main surface (35a) a wall surface (35b) and a lower main surface (35c), the wall surface (35b) having a gate insulating film (39) and a gate electrode (41) in a sequential order at least in a direction extending from the upper main surface (35a) to the lower main surface (35c), the wall surface (35b) being provided, on both sides of the portions thereof corresponding to the gate insulating film (39) and gate electrode (41), with inpurity diffusion regions for forming of source and drain, respectively.Accordingly, the gate electrode (41) is provided in a manner that the gate width which needs to have a relatively large size is set in a direction vertical to the upper main surface of the base layer. This makes it possible to improve the degree of integration effectively.