Patents by Inventor Toshiyuki Ohkoda
Toshiyuki Ohkoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7439578Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.Type: GrantFiled: December 28, 2006Date of Patent: October 21, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuhiro Takeda, Mitsuaki Morigami, Satoru Shimada, Kazuhiro Yoshitake, Shuichi Kikuchi, Seiji Otake, Toshiyuki Ohkoda
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Publication number: 20070166925Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.Type: ApplicationFiled: December 28, 2006Publication date: July 19, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yasuhiro Takeda, Mitsuaki Morigami, Satoru Shimada, Kazuhiro Yoshitake, Shuichi Kikuchi, Seiji Otake, Toshiyuki Ohkoda
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Publication number: 20070096294Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.Type: ApplicationFiled: November 8, 2006Publication date: May 3, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Osamu Ikeda, Toshiyuki Ohkoda
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Patent number: 7154173Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.Type: GrantFiled: May 28, 2004Date of Patent: December 26, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Osamu Ikeda, Toshiyuki Ohkoda
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Patent number: 7045866Abstract: This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data “1” or “0” in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.Type: GrantFiled: November 5, 2004Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Toshimitsu Taniguchi, Toshiyuki Ohkoda
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Patent number: 6960797Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 ?·cm.Type: GrantFiled: December 17, 2002Date of Patent: November 1, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeaki Okawa, Toshiyuki Ohkoda
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Patent number: 6927442Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.Type: GrantFiled: December 26, 2002Date of Patent: August 9, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Patent number: 6924534Abstract: The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-well 3A and a second N-well 3B are formed deeply on a surface of a P-type semiconductor substrate. A first P-well 4A is formed in the first N-well 3A, and an N-channel MOS transistor is formed in the first P-well 4A. The second N-well 3B is used as a collector of a vertical NPN bipolar transistor. A second P-well 4B is formed in the second N-well 3B. The second P-well 4B is formed simultaneously with the first P-well 4A. The second P-well 4B is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-well 4B.Type: GrantFiled: April 2, 2004Date of Patent: August 2, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Kazutomo Goshima, Toshiyuki Ohkoda, Toshimitsu Taniguchi
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Publication number: 20050151205Abstract: This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data “1” or “0” in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.Type: ApplicationFiled: November 5, 2004Publication date: July 14, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Toshimitsu Taniguchi, Toshiyuki Ohkoda
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Patent number: 6881997Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.Type: GrantFiled: December 26, 2002Date of Patent: April 19, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20050056898Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.Type: ApplicationFiled: October 20, 2004Publication date: March 17, 2005Applicant: Sanyo Electric Co., Ltd., a Osaka Japan CorporationInventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Patent number: 6864543Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N?S and/or a second drain layer N?D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.Type: GrantFiled: December 26, 2002Date of Patent: March 8, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Patent number: 6864525Abstract: A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.Type: GrantFiled: December 26, 2002Date of Patent: March 8, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20050012169Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.Type: ApplicationFiled: May 28, 2004Publication date: January 20, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Osamu Ikeda, Toshiyuki Ohkoda
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Publication number: 20040256678Abstract: The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-well 3A and a second N-well 3B are formed deeply on a surface of a P-type semiconductor substrate. A first P-well 4A is formed in the first N-well 3A, and an N-channel MOS transistor is formed in the first P-well 4A. The second N-well 3B is used as a collector of a vertical NPN bipolar transistor. A second P-well 4B is formed in the second N-well 3B. The second P-well 4B is formed simultaneously with the first P-well 4A. The second P-well 4B is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-well 4B.Type: ApplicationFiled: April 2, 2004Publication date: December 23, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Kazutomo Goshima, Toshiyuki Ohkoda, Toshimitsu Taniguchi
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Patent number: 6822298Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.Type: GrantFiled: December 26, 2002Date of Patent: November 23, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20030173609Abstract: A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.Type: ApplicationFiled: December 26, 2002Publication date: September 18, 2003Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20030164511Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.Type: ApplicationFiled: December 26, 2002Publication date: September 4, 2003Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20030155614Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.Type: ApplicationFiled: December 26, 2002Publication date: August 21, 2003Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20030146476Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.Type: ApplicationFiled: December 26, 2002Publication date: August 7, 2003Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono