Abstract: A conventional biometric authentication system has been time-consuming and labor-intensive for users since the users are requested to re-register their biometric information. According to an aspect of the present disclosure, a biometric authentication system includes an update value generation unit configured to generate an update value, a first update processing unit configured to update, using the update value, a template generated based on biometric information, and a second update processing unit configured to update, using the update value, a verification key generated along with the template based on the biometric information using the update value.

Abstract: A speed limit violation control system of the present disclosure includes: imaging units (320, 330) which image a running vehicle; recorder (420) that records one of videos imaged by the imaging units (320, 330); and controller (360) that calculates a speed of the vehicle based on the videos of imaging units (320, 330) and determines a starting point and an ending point of the one of the videos, which is to be recorded in recorder (420), based on the calculated speed.

Abstract: A speed limit violation control system of the present disclosure includes: imaging units (320, 330) which image a running vehicle; recorder (420) that records one of videos imaged by the imaging units (320, 330); and controller (360) that calculates a speed of the vehicle based on the videos of imaging units (320, 330) and determines a starting point and an ending point of the one of the videos, which is to be recorded in recorder (420), based on the calculated speed.

Abstract: Upon receipt of a packet addressed to a virtual IP address assigned to each first device from a second device outside a base network, a processor identifies a base relay apparatus that accommodates the first device, to which the virtual IP address is assigned, on the basis of the virtual address and a protocol type of the received packet, and also identifies a reception port number of the identified base relay apparatus, which corresponds to a combination of the virtual IP address and the protocol type of the received packet, from among reception port numbers each assigned to a combination of the first device accommodated to identify a transfer destination, and a protocol type. Then, the processor relays the received packet to the identified reception port number of the identified base relay apparatus.

Abstract: Upon receipt of a packet addressed to a virtual IP address assigned to each first device from a second device outside a base network, a processor identifies a base relay apparatus that accommodates the first device, to which the virtual IP address is assigned, on the basis of the virtual address and a protocol type of the received packet, and also identifies a reception port number of the identified base relay apparatus, which corresponds to a combination of the virtual IP address and the protocol type of the received packet, from among reception port numbers each assigned to a combination of the first device accommodated to identify a transfer destination, and a protocol type. Then, the processor relays the received packet to the identified reception port number of the identified base relay apparatus.

Abstract: The present invention provides an electronic device capable of displaying a remaining capacity of a battery 1 that includes a battery microcomputer 2 capable of outputting battery information including remaining capacity information. The device includes: a main body microcomputer 4 that obtains the battery information from the battery microcomputer 2, and calculates a remaining capacity actual value representing an actual remaining capacity of the battery 1 based on the battery information; and a display portion 5 that displays the remaining capacity of the battery 1 under the control of the main body microcomputer 4.

Abstract: The invention provides a demultiplexer which does not require a reset circuit for setting initial values for outputs and can define a bit for each output terminal. Rising edges of delay outputs 8-1 to 11-1 from non-inverted output terminals Q of MS-DFFs (master-slave D-type flipflops) 6-1 to 6-4 are successively delayed in order of the cascade connection. After the outputs from output terminals Q are outputted, delay outputs 8-2 to 11-2 are outputted successively from the inverted output terminals of the MS-DFFs beginning with the inverted output terminal of MS-DFF 6-1 at the top. In a timed relationship with the timings of the delay outputs, MS-DFFs 4-1 to 4-4 and MSM-DFFs 5-1 go 5-4 extract corresponding input signals 12 to 19 from within multiplexed input signal 22. MS-DFFs 4-5 to 4-12 output input signals 12 to 19 at a same timing as demultiplexed outputs demultiplexed to 1:8.