Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.

Abstract: There is provided a semiconductor device including: a circuit region formed on one surface of a semiconductor substrate; a connection portion disposed at the one surface, the connection portion covering the circuit region, being electrically connected to the circuit region, and being used to connect with an exterior device; an annular wire formed at the one surface so as to surround the circuit region; a first protective film covering the annular wire, the first protective film being formed between the connection portion and a peripheral edge portion of the semiconductor substrate; and a second protective film formed at a predetermined partial region on the connection portion.

Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.

Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.

Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: A control electrode is provided via an insulating film on one main surface of a semiconductor substrate having a first conductivity type. A pair of dopant diffusion regions are formed, with the control electrode therebetween, in a surface layer region of the semiconductor substrate. Resistance variation sections are formed in the surface layer region of the semiconductor substrate between the control electrode and the dopant diffusion regions. The resistance variation sections are of the second conductivity type and have a dopant concentration lower than that of the dopant diffusion regions. First and second main electrodes are provided on the dopant diffusion regions of the semiconductor substrate. A first charge storage section is provided between the first main electrode and control electrode on the semiconductor substrate. A second charge storage section is provided between the second main electrode and control electrode on the semiconductor substrate.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: Heavily concentrated impurities are selectively introduced into an exposed region of an oxide film. The exposed region of the oxide film where the impurities are introduced is selectively etched so that a surface of the semiconductor substrate is exposed An oxidizing process is performed and a second oxide film is formed on the first oxide film and the exposed surface of the semiconductor substrate. A polysilicon layer is formed as the floating gate.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.

Abstract: Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a hole, thereafter, the etching rate decreases. Accordingly even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.