Abstract: The current paths of column selection transistors are inserted between a pair of input nodes, on the one hand, of a sense amplifier constituted by a current-mirror type differential amplifier, and column lines, on the other hand. The current paths of transistors for clamping column potential are inserted between the input nodes of the sense amplifier, on the one hand, and a power source, on the other. The gates of the transistors for clamping column potential are supplied with a bias potential lower than the potential of the power source. When data is read out from selected memory cells, the potential of the input nodes of the sense amplifier is clamped to a value lower than the potential Vcc of the power source by the transistors for clamping column potential. The storage data in the selected memory cells is input directly to the input nodes of the sense amplifier through the current paths of the column selection transistors.