Abstract: The present invention relates to novel quinoline derivatives and quinazoline derivatives represented by the following formula (I): ##STR1## [wherein R.sub.1 and R.sub.2 are each independently H or C.sub.1 -C.sub.4 -alkyl, or R.sub.1 and R.sub.2 together form C.sub.1 -C.sub.3 -alkylene, X is O, S or CH.sub.2, W is CH or N, and Q is a substituted aryl group or substituted heteroaryl group] and their pharmaceutically acceptable salts, having platelet-derived growth factor receptor autophosphorylation inhibitory activity, to pharmaceutical compositions containing these compounds, and to methods for the treatment of diseases associated with abnormal cell growth such as tumors.

Abstract: A status management unit manages a free status capable of invoking a process switch and a critical status. When a process currently being executed is in an input/output process or in a critical status during a message communication, a switch control means controls a control signal for a process switch, such that a process switch does not take place.

Abstract: A polyester resin having a glass transition temperature of not less than 15.degree. C. and a reduced viscosity of 0.15-1.5, which comprises a graft polymer comprising a polyester having an unsaturated bond as a main chain, and a radical polymerizable unsaturated monomer as a side chain, and a sublimation transfer image receiver which comprises a dyeable layer mainly comprising a dyeable resin comprising the polyester resin. Inasmuch as the polyester resin can provide highly sensitive images without the use of a plasticizer or an additive, it is suitable as a dyeable resin for a sublimation transfer image receiver. The images obtained by the use of a sublimation transfer image receiver having a dyeable layer containing this resin are superior in durability and preservation stability.

Abstract: In a battery comprising a spirally wound electrode group, a lead plate drawn from one electrode of the electrode group and connected to the inner bottom surface of the battery case in electrically conducting relationship, and an insulating plate interposed between the lead plate and the electrode group, at least the bottom surface of the insulating plate is formed from a heat weldable material, and the lead plate is heat-welded to this heat weldable material. This construction not only serves to completely prevent accidental short-circuiting, but enables high-speed assembling of batteries.

Abstract: A chromium-free composition for treating metal surface comprising (a) a hydroxyl group-containing organic resin, (b) a phosphoric acid and (c) at least one of ions and compounds of at least one metal selected from the group consisting of Cu, Co, Fe, Mn, Sn, V, Mg, Ba, Al, Ca, Sr, Nb, Y and Zn, and (d) at least one of colloids (sol) or powders of SiO.sub.2, SnO.sub.2, Fe.sub.2 O.sub.3, Fe.sub.3 O.sub.4, MgO, ZrO.sub.2, Al.sub.2 O.sub.3 and Sb.sub.2 O.sub.5 ; as well as a metal sheet or metal article having thereon (i) a coating film of the chromium-free composition and optionally (ii) a coating film of a coating composition comprising an organic resin and if desired a colloid (sol) or a powder.

Abstract: A non-aqueous electrolyte cell has an electrode assembly including a negative electrode strip, a positive electrode strip having an active cathode material, and a separator. The positive electrode strip and the negative electrode strip are superposed with the separator therebetween and wound in a spiral. The negative electrode strip is disposed outside the positive electrode strip and has an outermost winding, a negative electrode strip winding end, and a penultimate winding. The positive electrode strip has an outermost winding terminating at a positive electrode strip winding end. An anode current collector contacts the negative electrode strip on the penultimate winding and is radially aligned with a portion of the outermost winding of the positive electrode strip.

Abstract: Data transmission control apparatus which controls data transmission between processing systems via a transmission line, each processing system including a memory system consisting of a main memory and a cache memory. The apparatus addresses data in the main memory by a memory address and gives an instruction to transmit the addressed data; determines whether or not the addressed data is in the cache memory; provides a match signal when the data is in the cache memory; reads the addressed data from the cache memory when instructed by the instruction and when a ready signal and the match signal are provided, and, otherwise reads the addressed data from the main memory; writes the data read into a port; transmits the data written in the port to the another processing system connected to the transmission line; and provides the ready signal when the port is ready to receive additional data.

Abstract: In a large system such as a parallel computer system, a scan device forms a scan path by hierarchically connecting input and output signal lines of integrated circuits, thereby enabling creating of a short scan path which contain only the necessary integrated circuits. This allows a scan test such as JTAG-SCAN to be effectively made.

Abstract: In a battery comprising a spirally wound electrode group, a lead plate drawn from one electrode of the electrode group and connected to the inner bottom surface of the battery case in electrically conducting relationship, and an insulating plate interposed between the lead plate and the electrode group, at least the bottom surface of the insulating plate is formed from a heat weldable material, and the lead plate is heat-welded to this heat weldable material. This construction not only serves to completely prevent accidental short-circuiting, but enables high-speed assembling of batteries.

Abstract: A data transfer system which improves efficiency in direct data transfer from an input device with a first-in first-out (FIFO) memory serving as a buffer to a memory and from a memory to an output device with a first-in first-out (FIFO) memory serving as a buffer. The data is transferred from the input device to the memory and from the memory to the output device by meeting the requirement of address alignment without restricting data transfer to fixed multiples of, for example, four words. A memory write controller is informed as to how much data is present in the buffer in the input device. The controller checks memory address alignment to determine the transfer size of data from the input device to the memory. A memory read controller is also informed as to how much free space is present in the buffer in the output device and checks the memory address alignment to determine the transfer size of data from the memory to the output device.

Abstract: An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold.Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/scattering system includes: one processor having a buffer for temporarily storing data gathered from or transmitted to other processors, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system; each of the other processors having a buffer for temporarily storing data to be transferred or data to be received, a transfer control unit for controlling data transmissions from the buffer to the common bus, a reception control unit for selecting the reception data from among all data on the common bus, a three-state buffer for transmitting data from the buffer to the common bus, and a switching un

Abstract: A storage region formed of a nonvolatile storage device is divided into two blocks; block `0` and block `1`. In a process for writing data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have a correct value, the sequential Nos. of the blocks `0` and `1` are compared so as to select the block whose sequential No. has a smaller value. The data to-be-written is written into the selected block. Subsequently, a value obtained by adding "1" to the sequential No. of the unselected block is written as the sequential No. of the selected block. Lastly, the magic No. is written into the selected block. On the other hand, in a process for reading data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have the correct value, the block whose sequential No. has a larger value is selected, and the data to-be-read is read out of the selected block.

Abstract: A receiving buffer control system comprises a memory having a buffer area serving as a receiving buffer, data being applied to the memory via a bus, a write pointer indicating a write address of the buffer area, and a read pointer indicating a read address of the buffer area. An overrun/underrun detection circuit detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.

Abstract: When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.

Abstract: The grafting reaction product of the present invention includes a main chain having a polymer selected from one of a polyester and a polyester polyurethane consisting mainly of the polyester, the polyester containing 60 mole % or more of an aromatic dicarboxylic acid for the amount of the total carboxylic acids. The grafting reaction product further includes a plurality of side chains which are polymers of radical polymerizable monomers, said radical polymerizable monomers having at least 30% by weight of the combination of at least one electron accepting monomers (A) having an e value of 0.9 or more and at least one electron donative monomers (B) having an e value of -0.6 or less for the amount of the total radical polymerizable monomers, and at least 10% by weight of an aromatic radical polymerizable monomer for the amount of the total radical polymerizable monomers. According to the present invention, the plurality of side chains are grafted into the main chain to form the grafting reaction product.

Abstract: A range-finding system for measuring a target distance from a point of measurement to a target object, comprising a slave unit for calculating and indicating the target distance based on a waiting time from transmission of an interrogation signal to reception of a response signal and a master unit placed at a certain correction distance from the target object for transmitting the response signal when a delay time corresponding to the correction distance has elapsed from reception of the interrogation signal.

Abstract: An aqueous dispersion of a graft-copolymer (A), dispersed in water or a mixed solvent (B) of water and a water-soluble organic solvent, the graft-copolymer (A) comprising a polyester (A-a) graft-polymerized with a radical copolymerizable monomer (A-b) comprising a radical copolymerizable monomer having a hydrophilic group, wherein said graft-copolymer (A) is dispersed as fine particles having an average particle size of not more than 500 nm and a half band width of a signal of a carbon of a carbonyl group of the polyester, as determined by .sup.13 C-NMR, is not less than 300 Hz. The aqueous polyester dispersion of the present invention is superior in re-dispersibility and when a paint prepared from the dispersion is coated on a metal or a plastic, the coated film shows superior appearance, processability and water resistance. Accordingly, the aqueous dispersion of the present invention serves well for use for paints, ink, coating agents, adhesives and various treating agents.

Abstract: By measuring the waveform of the reflected wave obtained by transmitting a pulse to an open-ended transmission line, a transfer function of the transmission line with respect to the incident wave is computed as a result of the measurement. Then, the waveform of the output wave at the output end or the open end of the transmission line is estimated in response to an individual input signal by using the transfer function computed. The transmission delay time of the transmission line is obtained by computing the time difference between the transient timing of the estimated waveform of the output wave and the transient timing of the waveform of the input signal.