Patents by Inventor Toshiyuki Shinya

Toshiyuki Shinya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8466540
    Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 18, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Tanaka, Masakazu Sakano, Toshiyuki Shinya, Takafumi Konno, Kazuaki Yoshida, Takashi Sato, Atsushi Fujisawa
  • Publication number: 20100193923
    Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.
    Type: Application
    Filed: January 26, 2010
    Publication date: August 5, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Shigeki Tanaka, Masakazu Sakano, Toshiyuki Shinya, Takafumi Konno, Kazuaki Yoshida, Takashi Sato, Atsushi Fujisawa
  • Publication number: 20080268576
    Abstract: A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.
    Type: Application
    Filed: July 9, 2008
    Publication date: October 30, 2008
    Inventors: Syuudai Fukaya, Toshiyuki Shinya, Hajime Hasebe
  • Patent number: 7410834
    Abstract: A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Syuudai Fukaya, Toshiyuki Shinya, Hajime Hasebe
  • Publication number: 20050139982
    Abstract: A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 30, 2005
    Inventors: Syuudai Fukaya, Toshiyuki Shinya, Hajime Hasebe