Abstract: A stepping motor includes two coils and has supply currents to the two coils with different phases so that a rotor is rotated by the two coils. During a period where one coil is in a high impedance state, an induced voltage generated at that coil is detected. An output control circuit controls the magnitude of motor drive current supplied to the two coils in accordance with the detected induced voltage state. Then, prior to entering the high impedance state from the drive state, a short-circuit period is provided for short circuiting both terminals of the coil.

Abstract: A stepping motor includes two coils and has supply currents to the two coils with different phases so that a rotor is rotated by the two coils. During a period where one coil is in a high impedance state, an induced voltage generated at that coil is detected. An output control circuit controls the magnitude of motor drive current supplied to the two coils in accordance with the detected induced voltage state. Then, prior to entering the high impedance state from the drive state, a short-circuit period is provided for short circuiting both terminals of the coil.

Abstract: A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit delays delay subject signals by a predetermined amount to generate delay signals. A delay amount for the delay circuit is controlled by a delay amount control circuit. A logic circuit generates a recording pulse by logically synthesizing the delay signals. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements having the same configuration as the delay elements included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element becomes a fraction of an integer of one cycle of a reference clock signal.

Abstract: A data recording controller for properly adding data to a disc medium. The controller includes a data location counter for performing counting in synchronism with reproduction of data written to an optical disc. An LPP location counter performs counting in synchronization with reproduction of a disc address recorded to the optical disc. A detection circuit detects the difference between a data format address recorded to the optical disc and an optical disc address recorded to the optical disc from count values of the two counters. A control unit calculates a recording initiation address from the detected difference. A timing control circuit determines a timing for starting the recording of additional data from the recording initiation address.

Abstract: A data processor compatible for use with a CD and a DVD includes a first modulation circuit for modulating recording data for recording on a CD to generate first modulated data. A second modulation circuit modulates recording data for recording on a DVD to generate second modulated data. A write signal generation circuit generates a first write signal, which is written to the CD, from the first modulated data, and a second write signal, which is written to the DVD, from the second modulated data. The write signal generation circuit is commonly used for the CD and the DVD to reduce the circuit area of the data processor.

Abstract: A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.

Abstract: A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

Abstract: A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.

Abstract: A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit (220) delays delay subject signals S1 to S4 by a predetermined amount to generate delay signals D1 to D4. A delay amount for the delay circuit (220) is controlled by a delay amount control circuit (210). A logic circuit (300) generates a recording pulse by logically synthesizing the delay signals D1 to D4. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements (211a) having the same configuration as the delay elements (221) included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element (211a) becomes a fraction of an integer of one cycle of a reference clock signal.

Abstract: A data recording controller for properly adding data to a disc medium. The controller includes a data location counter for performing counting in synchronism with reproduction of data written to an optical disc. An LPP location counter performs counting in synchronization with reproduction of a disc address recorded to the optical disc. A detection circuit detects the difference between a data format address recorded to the optical disc and an optical disc address recorded to the optical disc from count values of the two counters. A control unit calculates a recording initiation address from the detected difference. A timing control circuit determines a timing for starting the recording of additional data from the recording initiation address.

Abstract: A data processor compatible for use with a CD and a DVD includes a first modulation circuit for modulating recording data for recording on a CD to generate first modulated data. A second modulation circuit modulates recording data for recording on a DVD to generate second modulated data. A write signal generation circuit generates a first write signal, which is written to the CD, from the first modulated data, and a second write signal, which is written to the DVD, from the second modulated data. The write signal generation circuit is commonly used for the CD and the DVD to reduce the circuit area of the data processor.

Abstract: A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.