Patents by Inventor Toshiyuki Take

Toshiyuki Take has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10489696
    Abstract: An article allows an engraved code to be detected. The engraved code includes a plurality of dot dented portions defined on the article. Each of the dot dented portions has a quadrilateral pyramid shape with a coating layer on a prior stage dented portion having a quadrilateral pyramid shape. Corner dented portions dented at acute angles outward along a diagonal direction are defined at four corner positions of an opening peripheral edge portion of the prior stage dented portion.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 26, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Yasushi Suzuki, Toshiyuki Take, Takashi Murakami, Kokichi Nakayama, Kazushi Imamura
  • Patent number: 10489697
    Abstract: An engraved code includes a plurality of dot dented portions defined on an article. The engraved code includes an opening peripheral edge portion of each of the dot dented portions which has a polygonal or quadrilateral shape. This configuration leads to detection of each dot dented portion as a polygonal or quadrilateral dot.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 26, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Kazushi Imamura, Yasushi Suzuki, Kokichi Nakayama, Takashi Murakami, Toshiyuki Take
  • Publication number: 20180197054
    Abstract: A managed article that allows an engraved code to be detected. The engraved code including a plurality of dot dented portions is formed on a managed article. Each of the dot dented portions has a quadrilateral pyramid shape with a coating layer formed on a prior stage dented portion (15) having a quadrilateral pyramid shape. Corner dented portions (25) dented at acute angles outward along a diagonal direction are formed at four corner positions of an opening peripheral edge portion (22) of the prior stage dented portion. This configuration leads to detection of the dot dented portion as a quadrilateral dot. In addition, the present configuration allows a coating material to be introduced into the corner dented portions at the time of the coating, thereby contributing to preventing or reducing inward projection of the coating layer at the corner positions of the dot dented portion.
    Type: Application
    Filed: June 14, 2016
    Publication date: July 12, 2018
    Inventors: Yasushi SUZUKI, Toshiyuki TAKE, Takashi MURAKAMI, Kokichi NAKAYAMA, Kazushi IMAMURA
  • Publication number: 20180174007
    Abstract: Provided is a managed article that allows an engraved code to be excellently detected. An engraved code 11including a plurality of dot dented portions 15 is forced: on a managed article 10. The engraved code 11 includes. An opening peripheral edge portion 22 of each of the dot dented portions 15 has a quadrilateral shape. This configuration leads to detection of the dot dented portion as a quadrilateral dot. Therefore, this configuration allows the engraved code to be excellently detected.
    Type: Application
    Filed: June 14, 2016
    Publication date: June 21, 2018
    Inventors: Kazushi IMAMURA, Yasushi SUZUKI, Kokichi NAKAYAMA, Takashi MURAKAMI, Toshiyuki TAKE
  • Patent number: 7119424
    Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: October 10, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Isao Ochiai, Toshiyuki Take, Tetsuya Fukushima
  • Patent number: 6893903
    Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: May 17, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Isao Ochiai, Toshiyuki Take, Tetsuya Fukushima
  • Publication number: 20040222513
    Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 11, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Isao Ochiai, Toshiyuki Take, Tetsuya Fukushima
  • Publication number: 20030143779
    Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.
    Type: Application
    Filed: January 29, 2003
    Publication date: July 31, 2003
    Inventors: Isao Ochiai, Toshiyuki Take, Tetsuya Fukushima
  • Patent number: 6252252
    Abstract: A mold 25 for molding semiconductor chips 23 and 24 serving as a light emitting element and a light receiving element, respectively, is made of a material capable of transmitting light. A groove 27 is formed on the region where light is emitted from and incident on the semiconductor chips so that it constitutes a reflecting face. Thus, the light is emitted and incident through the side E of the mold. In this configuration, the outer size of the light receiving element or light emitting element can be minimized, and the module provided with these semiconductor chips can also be miniaturized.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: June 26, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideo Kunii, Toshiyuki Take, Hiroshi Inoguchi, Tsutomu Ishikawa, Masashi Arai, Hiroshi Kobori, Hiroki Seyama, Kiyoshi Takada, Satoru Sekiguchi