Abstract: The present invention provides a collagen solid having higher strength and density. A collagen solid is used which contains a collagen-cysteine protease degradation product or an atelocollagen-cysteine protease degradation product and has a density of 50 mg/cm3 or more.

Abstract: A semiconductor device includes: a gate electrode disposed in the inside of a trench via a gate insulating film; a shield electrode positioned between the gate electrode and a bottom of the trench; an electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along a side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+-type source region, and electrically connected to the shield electrode on both end portions of the trench as viewed in a plan view, wherein the shield electrode has high resistance regions positioned at both end portions of the trench as viewed in a plan view, and a low resistance region positioned at a position sandwiched by the high resistance regions.

Abstract: Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n+ drain region side, and a low resistance region positioned on a gate electrode side.

Abstract: A semiconductor apparatus includes: a gate electrode in a trench and facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode in the trench and between the gate electrode and a bottom of the trench; an electric insulating region in the trench, the electric insulating region extending between the gate electrode and the shield electrode, and further extending along the side wall and the bottom of the trench to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode. The shield electrode has high resistance regions at positions where the high resistance regions face the side walls of the trench, and a low resistance region at a position where the low resistance region is sandwiched between the high resistance regions.

Abstract: A semiconductor apparatus includes: a gate electrode in a trench and facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode in the trench and between the gate electrode and a bottom of the trench; an electric insulating region in the trench, the electric insulating region extending between the gate electrode and the shield electrode, and further extending along the side wall and the bottom of the trench to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode. The shield electrode has high resistance regions at positions where the high resistance regions face the side walls of the trench, and a low resistance region at a position where the low resistance region is sandwiched between the high resistance regions.

Abstract: Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n+ drain region side, and a low resistance region positioned on a gate electrode side.

Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

Abstract: A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

Abstract: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the n-type epitaxial layer (12) so as to be in contact with side surfaces of the trench (14). The trench gate power MOSFET (1) further includes a p-type isolation region (26) formed on the surface of the n-type epitaxial layer (12) and disposed between the MOSFET cells adjacent to each other in the extending direction of the trench (14) out of the MOSFET cells, and has a pn-junction diode formed between the p-type isolation region (26) and the n-type epitaxial layer (12). According to the trench gate power MOSFET (1) of the present invention, the increase of a diode leakage current with the elevation of temperature can be suppressed.

Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.

Abstract: A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.

Abstract: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

Abstract: An example semiconductor device is capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even if the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench and then impurities are injected to the bottom surface of the source trench. When the impurities are heated and diffused, the buried P+-type diffusion region is formed with a width almost identical to the width of the opening of the source trench or smaller than the width of the opening of the source trench. Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region with the gate trench.

Abstract: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

Abstract: A technique is provided which makes it possible to reduce the area of a power MOSFET. A power MOSFET 1 according to the invention is a trench type in which a source region 27 is exposed on both of a substrate top surface 51 and an inner circumferential surface 52 of a trench 18. Since this makes it possible to provide contact between the source region 27 and a source electrode film 29 not only on the substrate top surface 51 but also on the inner circumferential surface 52 of the trench 18, source contact is provided with a sufficiently low resistance only on the substrate top surface, and the area of the device can be made smaller than that in the related art in which the source region 27 has been formed in a larger area.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.