Patents by Inventor Toshiyuki Tanahashi
Toshiyuki Tanahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10594110Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.Type: GrantFiled: November 13, 2018Date of Patent: March 17, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
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Publication number: 20190148914Abstract: A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×1016 cm?3 or more to 5×1016 cm?3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.Type: ApplicationFiled: November 13, 2018Publication date: May 16, 2019Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Toshiyuki Tanahashi, Takashi Ishizuka, Susumu Yoshimoto, Takamichi Sumitomo, Koji Nishizuka, Suguru Arikata
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Publication number: 20190044306Abstract: A vertical cavity surface emitting laser includes: an active layer; a first laminate for a first distributed Bragg reflector; and a first intermediate layer disposed between the active layer and the first laminate. The first intermediate layer has first and second portions. The first laminate, the first and second portions of the first intermediate layer, and the active layer are arranged along a direction of a first axis. The first laminate and the first portion of the first intermediate layer each include a first dopant. The active layer has a first-dopant concentration of less than 1×1016 cm?3. The first portion of the first intermediate layer has a first-dopant concentration smaller than that of the first laminate. The second portion of the first intermediate layer has a first-dopant concentration smaller than that of the first portion of the first intermediate layer.Type: ApplicationFiled: July 30, 2018Publication date: February 7, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Toshiyuki TANAHASHI, Takashi ISHIZUKA, Susumu YOSHIMOTO, Takamichi SUMITOMO, Koji NISHIZUKA, Kei FUJI, Suguru ARIKATA
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Patent number: 9373939Abstract: A method for manufacturing a semiconductor device comprising the steps of: growing a stacked semiconductor layer on a substrate, the stacked semiconductor layer including an active layer and a cladding layer; forming a mesa structure by etching the stacked semiconductor layer, the mesa structure extending in a [011] direction; and forming a buried layer of Fe-doped InP on the side surface of the mesa structure in a reactor of an organo-metallic vapor phase epitaxy apparatus while supplying a hydrogen chloride gas into the reactor. In the step of forming the buried layer, the hydrogen chloride gas is supplied from the beginning of forming the buried layer. The buried layer has a first region and a second region. The first region has a front surface of a (311)B plane. The second region is formed on the front surface. The Fe concentration of the first region is higher than that of the second region.Type: GrantFiled: June 5, 2015Date of Patent: June 21, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroki Mori, Toshiyuki Tanahashi
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Publication number: 20150357793Abstract: A method for manufacturing a semiconductor device comprising the steps of: growing a stacked semiconductor layer on a substrate, the stacked semiconductor layer including an active layer and a cladding layer; forming a mesa structure by etching the stacked semiconductor layer, the mesa structure extending in a [011] direction; and forming a buried layer of Fe-doped InP on the side surface of the mesa structure in a reactor of an organo-metallic vapor phase epitaxy apparatus while supplying a hydrogen chloride gas into the reactor. In the step of forming the buried layer, the hydrogen chloride gas is supplied from the beginning of forming the buried layer. The buried layer has a first region and a second region. The first region has a front surface of a (311)B plane. The second region is formed on the front surface. The Fe concentration of the first region is higher than that of the second region.Type: ApplicationFiled: June 5, 2015Publication date: December 10, 2015Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroki MORI, Toshiyuki TANAHASHI
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Patent number: 5621748Abstract: A method for fabricating a laser diode, comprises the steps of: forming a first stripe structure defined by a plurality of crystallographically distinct surfaces on a surface of a semiconductor substrate; forming an epitaxial layer of InGaAlP on the semiconductor substrate including the first stripe structure by a decomposition of gaseous source materials of In, Ga, Al and P; wherein the InGaAlP layer is doped to the p-type by incorporating Mg while growing the InGaAlP by adding a gaseous source material of Mg into said source materials of In, Ga, Al and P such that the InGaAlP layer is doped to the p-type with a substantially uniform carrier concentration level irrespective of the crystal surfaces forming the stripe structure.Type: GrantFiled: April 24, 1995Date of Patent: April 15, 1997Assignee: Fujitsu LimitedInventors: Makoto Kondo, Akira Furuya, Chikashi Anayama, Mami Sugano, Kay Domen, Toshiyuki Tanahashi, Hiroshi Sekiguchi
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Patent number: 5436194Abstract: A method for fabricating a laser diode, comprises the steps of: forming a first stripe structure defined by a plurality of crystallographically distinct surfaces on a surface of a semiconductor substrate; forming an epitaxial layer of InGaAlP on the semiconductor substrate including the first stripe structure by a decomposition of gaseous source materials of In, Ga, Al and P; wherein the InGaAlP layer is doped to the p-type by incorporating Mg while growing the InGaAlP by adding a gaseous source material of Mg into said source materials of In, Ga, Al and P such that the InGaAlP layer is doped to the p-type with a substantially uniform carrier concentration level irrespective of the crystal surfaces forming the stripe structure.Type: GrantFiled: April 15, 1994Date of Patent: July 25, 1995Assignee: Fujitsu LimitedInventors: Makoto Kondo, Akira Furuya, Chikashi Anayama, Mami Sugano, Kay Domen, Toshiyuki Tanahashi, Hiroshi Sekiguchi
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Patent number: 5375136Abstract: A semiconductor laser of a patterned-substrate type comprises the patterned-substrate having a sloped portion and a planar portion, and a plurality of semiconductor layers formed on the patterned-substrate including a heterostructure. By controlling condition for growing a specific semiconductor layer, a preferably ratio of a sloped portion thickness to a planar portion thickness of the semiconductor layer can be obtained, which enables a lasing current of the laser to be confined in a restricted region, and this results in obtaining a high efficiency and a high power output of the semiconductor laser.Type: GrantFiled: April 11, 1994Date of Patent: December 20, 1994Assignee: Fujitsu LimitedInventors: Chikashi Anayama, Toshiyuki Tanahashi, Makoto Kondo
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Patent number: 5336635Abstract: A semiconductor laser of a patterned-substrate type comprises the patterned-substrate having a sloped portion and a planar portion, and a plurality of semiconductor layers formed on the patterned-substrate including a heterostructure. By controlling condition for growing a specific semiconductor layer, a preferable ratio of a sloped portion thickness to a planar portion thickness of the semiconductor layer can be obtained, which enables a lasing current of the laser to be confined in a restricted region, and this results in obtaining a high efficiency and a high power output of the semiconductor laser.Type: GrantFiled: June 15, 1993Date of Patent: August 9, 1994Assignee: Fujitsu LimitedInventors: Chikashi Anayama, Toshiyuki Tanahashi, Makoto Kondo
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Patent number: 5255281Abstract: A semiconductor laser includes a substrate having a (100) face as its main surface, where the substrate has a stripe of a first mesa extending in a <110> direction of the substrate and including a (111)B face as its sloping surface, a buried layer formed on the substrate excluding a top surface of the stripe of the first mesa so that the (111)B face of the stripe of the first mesa is covered a sloping surface part of the buried layer, where the top surface of the stripe of the first mesa is the (100) face of the substrate and forms a stripe of a second mesa together with the sloping surface of the buried layer and the stripe of the second mesa has a smaller inclination than the stripe of the first mesa, and a double heterostructure made up of a plurality of semiconductor layers and formed on the stripe of the second mesa. The double heterostructure has a substantially trapezoidal cross section which is determined by the stripe of the second mesa.Type: GrantFiled: December 24, 1992Date of Patent: October 19, 1993Assignee: Fujitsu LimitedInventors: Mami Sugano, Akira Furuya, Toshiyuki Tanahashi, Makoto Kondo, Chikashi Anayama
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Patent number: 5202285Abstract: A semiconductor laser includes a substrate having a (100) face as its main surface, where the substrate has a stripe of a first mesa extending in a <110> direction of the substrate and including a (111)B face as its sloping surface, a buried layer formed on the substrate excluding a top surface of the stripe of the first mesa so that the (111)B face of the stripe of the first mesa is covered a sloping surface part of the buried layer, where the top surface of the stripe of the first mesa is the (100) face of the substrate and forms a stripe of a second mesa together with the sloping surface of the buried layer and the stripe of the second mesa has a smaller inclination than the stripe of the first mesa, and a double heterostructure made up of a plurality of semiconductor layers and formed on the stripe of the second mesa. The double heterostructure has a substantially trapezoidal cross section which is determined by the stripe of the second mesa.Type: GrantFiled: June 4, 1992Date of Patent: April 13, 1993Assignee: Fujitsu LimitedInventors: Mami Sugano, Akira Furuya, Toshiyuki Tanahashi, Makoto Kondo, Chikashi Anayama
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Patent number: 4592791Abstract: A liquid phase epitaxial growth method is disclosed wherein (111)A InP substrate is used for growing an epitaxial layer of Al.sub.x In.sub.1-x As or Al.sub.x Ga.sub.y In.sub.1-x-y As compound semiconductor by liquid phase epitaxy.Type: GrantFiled: November 21, 1983Date of Patent: June 3, 1986Assignee: Fujitsu LimitedInventors: Kazuo Nakajima, Toshiyuki Tanahashi