Patents by Inventor Toshiyuki Tani

Toshiyuki Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10967447
    Abstract: A metal wire containing tungsten is provided. A tungsten content of the metal wire is at least 90 wt %. A tensile strength of the metal wire is at least 4000 MPa. An elastic modulus of the metal wire is at least 350 GPa and at most 450 GPa. A diameter of the metal wire is at most 60 ?m. An average crystal grain size of the metal wire in a cross-section orthogonal to an axis of the metal wire is at most 0.20 ?m.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 6, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomohiro Kanazawa, Naoki Kohyama, Yoshihiro Iguchi, Yuuki Sasagawa, Tetsuji Shibata, Toshiyuki Tani
  • Publication number: 20190232404
    Abstract: A metal wire containing tungsten is provided. A tungsten content of the metal wire is at least 90 wt %. A tensile strength of the metal wire is at least 4000 MPa. An elastic modulus of the metal wire is at least 350 GPa and at most 450 GPa. A diameter of the metal wire is at most 60 ?m. An average crystal grain size of the metal wire in a cross-section orthogonal to an axis of the metal wire is at most 0.20 ?m.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomohiro KANAZAWA, Naoki KOHYAMA, Yoshihiro IGUCHI, Yuuki SASAGAWA, Tetsuji SHIBATA, Toshiyuki TANI
  • Patent number: 9337299
    Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: May 10, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Toshiyuki Tani, Akihiko Yamashita, Motoaki Kusamaki, Kentaro Takahashi
  • Publication number: 20150243757
    Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Inventors: Toshiyuki Tani, Akihiko Yamashita, Motoaki Kusamaki, Kentaro Takahashi
  • Patent number: 9059324
    Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
    Type: Grant
    Filed: June 30, 2013
    Date of Patent: June 16, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Toshiyuki Tani, Akihiko Yamashita, Motoaki Kusamaki, Kentaro Takahashi
  • Publication number: 20150001672
    Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
    Type: Application
    Filed: June 30, 2013
    Publication date: January 1, 2015
    Inventors: Toshiyuki Tani, Akihiko Yamashita, Motoaki Kusamaki, Kentaro Takahashi
  • Patent number: 8664080
    Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi, Lily Springer
  • Publication number: 20120299146
    Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: TOSHIYUKI TANI, HIROSHI YAMASAKI, KENTARO TAKAHASHI, LILY SPRINGER
  • Patent number: 8093622
    Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani
  • Patent number: 7678601
    Abstract: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: March 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Kazuhiko Watanabe, Tetsuya Tada, Toshiyuki Tani
  • Publication number: 20090032839
    Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 5, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani
  • Publication number: 20070172975
    Abstract: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Inventors: Hiroyuki Tomomatsu, Kazuhiko Watanabe, Tetsuya Tada, Toshiyuki Tani
  • Patent number: 6114730
    Abstract: Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Polysilicon 12 is formed on the side walls of the trench 5, and the metallic contaminants within the element forming region are collected in this polysilicon 12.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: September 5, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Toshiyuki Tani
  • Patent number: 4764824
    Abstract: Apparatus including a rotary head accurately reproduces a digital signal recorded on a tape, even when the tape runs at high speed. Transitions of a reproduced signal are detected, intervals corresponding to the transitions are counted on the basis of a predetermined reference signal, and the rotation of the rotary head is controlled in response to the counted value so that the relative speed between the rotary head and the tape is held constant, notwithstanding changes in the absolute speed of the tape, as in the fast-forward mode.
    Type: Grant
    Filed: March 20, 1986
    Date of Patent: August 16, 1988
    Assignee: Sony Corporation
    Inventors: Toshiyuki Tani, Yoshizumi Inazawa, Toshihiko Takahashi, Shigeyuki Satomura
  • Patent number: 4688115
    Abstract: An apparatus for reproducing digital signals recorded on a magnetic or other recording tape includes a servo mechanism which is effective, when the tape is transported at a high speed in either a fast-forward or rewind mode, to maintain a relative speed between the tape and a rotary head that is substantially the same as that in the normal playback mode. Moreover, in the rewind mode, the rotary head is rotated in the direction opposite to that in the normal playback mode, while the absolute value of the relative speed remains the same as that in the normal playback mode. Further, the digital signals reproduced by the rotary head in the rewind mode have their sequential order reversed.
    Type: Grant
    Filed: March 21, 1986
    Date of Patent: August 18, 1987
    Assignee: Sony Corporation
    Inventors: Toshihiko Takahashi, Yoshizumi Inazawa, Toshiyuki Tani, Shigeyuki Satomura
  • Patent number: 4641208
    Abstract: In a recording/reproducing apparatus, a program identifying number is recorded in a beginning portion of each of a sequence of programs recorded on a record medium during a first recording operation, and a program start signal is recorded in a beginning portion of each program recorded in a second recording operation and thereafter. Subsequently, in a renumbering operation, each of the recorded program identifying numbers and/or program start signals is detected, with high speed movement of the record medium therebetween, and the previously existing recorded program identifying numbers and/or program start signals are replaced by a properly ordered sequence of program identifying numbers on the record medium.
    Type: Grant
    Filed: December 11, 1985
    Date of Patent: February 3, 1987
    Assignee: Sony Corporation
    Inventors: Yoshizumi Inazawa, Toshihiko Takahashi, Toshiyuki Tani, Shigeyuki Satomura
  • Patent number: 4630142
    Abstract: Apparatus for reproducing digital signals recorded on a recording tape comprises a rotary drum about which a recording tape can be trained, a rotary head mounted in the drum, a transport mechanism for transporting the tape over the drum and rotating the head so that a relative speed is established between the head and the tape and the head scans the tape and generates reproduced digital signals in response to digital signals recorded on the tape, and a mode-control mechanism for controlling the transport mechanism so that the tape is transported over the drum at an absolute tape speed that can be varied. A servomechanism responsive to variations in the absolute tape speed adjusts the transport mechanism so that the head acquires a rotary speed such that the relative speed is restored to and maintained at a substantially constant value, not withstanding changes in the absolute tape speed effected under the control of the mode-control mechanism.
    Type: Grant
    Filed: October 25, 1985
    Date of Patent: December 16, 1986
    Assignee: Sony Corporation
    Inventors: Toshiyuki Tani, Yoshizumi Inazawa, Toshihiko Takahashi, Shigeyuki Satomura