Patents by Inventor Toshiyuki Tohda

Toshiyuki Tohda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7335581
    Abstract: A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which the bottom is located below the interface between the active region and the gate insulating film and then providing a gate electrode between the openings, depositing a first insulating film which covers the side and bottom surface of the opening, depositing a second insulating film over the first insulating film, shaping the first and second insulating films into a side wall spacer shape by etching to provide charge retention sections beside the gate electrode and providing diffusion areas at opposite sides of the gate electrode beneath the charge retention sections in the active region.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: February 26, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Saitoh, Masahiko Yanagi, Toshiyuki Tohda
  • Publication number: 20060223256
    Abstract: A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which the bottom is located below the interface between the active region and the gate insulating film and then providing a gate electrode between the openings, depositing a first insulating film which covers the side and bottom surface of the opening, depositing a second insulating film over the first insulating film, shaping the first and second insulating films into a side wall spacer shape by etching to provide charge retention sections beside the gate electrode and providing diffusion areas at opposite sides of the gate electrode beneath the charge retention sections in the active region.
    Type: Application
    Filed: April 4, 2006
    Publication date: October 5, 2006
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Saitoh, Masahiko Yanagi, Toshiyuki Tohda
  • Patent number: 6800922
    Abstract: An object of the present invention is to suppress a layer-peeling phenomenon in a semiconductor device comprising at least a ferroelectric layer and an upper electrode formed thereon while maintaining the electrical properties of the ferroelectric layer. The semiconductor device of the present invention is characterized in that an upper electrode and a ferroelectric layer have a convex region. By this constitution, a layer peeling can be suppressed. In the present invention, one convex region is formed on one layer, but a plurality of convex regions may be formed on one layer. Alternatively, a concave region may be formed in place of the convex region.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: October 5, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiyuki Tohda
  • Patent number: 6613680
    Abstract: A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first opening portion in the barrier film reaching the first insulating film; forming a second insulating film at least on the first insulating film in the first opening portion; and forming a second opening portion smaller than the first opening portion and reaching the conductive region by simultaneously boring a hole into the first insulating film and the second insulating film in the first opening portion.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: September 2, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiyuki Tohda, Isaku Arii
  • Publication number: 20020105018
    Abstract: An object of the present invention is to suppress a layer-peeling phenomenon in a semiconductor device comprising at least a ferroelectric layer and an upper electrode formed thereon while maintaining the electrical properties of the ferroelectric layer. The semiconductor device of the present invention is characterized in that an upper electrode and a ferroelectric layer have a convex region. By this constitution, a layer peeling can be suppressed. In the present invention, one convex region is formed on one layer, but a plurality of convex regions may be formed on one layer. Alternatively, a concave region may be formed in place of the convex region.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 8, 2002
    Inventor: Toshiyuki Tohda
  • Publication number: 20020039837
    Abstract: A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first opening portion in the barrier film reaching the first insulating film; forming a second insulating film at least on the first insulating film in the first opening portion; and forming a second opening portion smaller than the first opening portion and reaching the conductive region by simultaneously boring a hole into the first insulating film and the second insulating film in the first opening portion.
    Type: Application
    Filed: July 19, 2001
    Publication date: April 4, 2002
    Inventors: Toshiyuki Tohda, Isaku Arii
  • Patent number: 6046114
    Abstract: A method for producing a semiconductor device comprises forming a film to be etched, an organic antireflective film and a resist mask on a substrate in this order; and before etching the film to be etched, dry-etching the organic antireflective film into a predetermined configuration by use of the resist mask and an etching gas containing chlorine atom and oxygen atom with maintaining the substrate at such a temperature that allows deposition of a substance produced by reaction of the organic antireflective film with chlorine atom contained in the etching gas.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: April 4, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiyuki Tohda