Abstract: A semiconductor integrated circuit has a test circuit in which signal pad (15) to input a switching signal TM is formed on a non-mounting surface of a LSI and one group of signal pads (11 to 13) formed on the non-mounting surface and signal pads (16 to 18) formed on a mounting surface is selected based on a signal level of the switching signal TM.

Abstract: A semiconductor integrated circuit has a test circuit in which signal pad (15) to input a switching signal TM is formed on a non-mounting surface of a LSI and one group of signal pads (11 to 13) formed on the non-mounting surface and signal pads (16 to 18) formed on a mounting surface is selected based on a signal level of the switching signal TM.

Abstract: A large scale integrated circuit for a build off self-test and a device to be tested are mounted in a single socket so that their respective electrodes are in direct contact.

Abstract: A tester for testing a semiconductor IC circuit having multiple pins includes a timing signal generator and a test signal generator for outputting a test signal to an input pin of a semiconductor IC circuit. The timing signal generating device can supply timing signals to one or more of the test signal generating devices.

Abstract: In a dc test, a plurality of dc test devices are connected to a plurality of tester pins, respectively and, in a function test, a function test device is connected to the plurality of tester pins.

Abstract: Provided is a semiconductor device capable of performing a function test and a DC test including an output voltage test every time a test jig is sequentially caused to come in contact with pads of the semiconductor device. The semiconductor device comprises a principal plane (2) of a semiconductor substrate, and pads (3) provided on the principal plane (2). The principal plane (2) is provided with four probing areas (PA1) to (PA4) with which the test jig comes in contact. A large number of pads (3) include four sets of driving pads (3ab) for supplying a driving voltage, and four sets of boundary scanning pads (BSP) for performing boundary scan. Even if it comes in contact with any of the probing areas (PA1) to (PA4), the test jig comes in contact with the driving pads (3ab) and the boundary scanning pads (BSP).

Abstract: The present invention relates to a tester for testing a semiconductor IC circuit having multiple pins, comprising a timing signal generator, a test signal generator for outputting a test signal to an input pin of a semiconductor IC circuit.

Abstract: A film carrier includes a base film (1), a first interconnect line (5a) formed on the top surface of the base film (1) and connected to test pads (3), and a second interconnect line (5b) formed on the bottom surface of the base film (1) and connected to the test pads (3). After leads (6) are plated, connecting portions between the first interconnect line (5a) and other than one of the test pads which is associated with a pad which is to receive a power supply potential, and connecting portions between the second interconnect line (5b) and other than one of the test pads which is associated with a pad which is to receive a ground potential are severed using a laser and the like. Then, the film carrier is wound onto a reel, and the reel with the film carrier wound thereon is loaded into a burn-in apparatus. A potential supply portion of the burn-in apparatus applies the power supply potential to the first interconnect line (5a) and applies the ground potential to the second interconnect line (5b).

Abstract: A semiconductor device testing apparatus for a memory- built-in logic LSI or the like, which has a hardware configuration that test patterns for logic and memory sections of the semiconductor device can be described independently of each other.

Abstract: A bare chip (1) is rectangular, and has a front surface (1a) on the center of which semiconductor elements are integrated and a back surface. Notches (2) are formed on a side of the bare chip (1) according to the kind of the semiconductor elements integrated on the bare chip (1). The notches (2) are oblong and extend through the bare chip (1) from the front surface (1a) to the back surface. For example, assuming that the notch (2) represents "1" and a portion without the notch (2) represents "0", one-bit information is obtained according to the presence or absence of the notch (2). When detection of several portions is made, binary information according to a detection result, i.e., information regarding the type of the bare chip (1), is obtained. For detection of the presence or absence of the notch (2), the bare chip (1) is irradiated with light, and then whether the light goes through the notch (2) or is intercepted by the bare chip (1) is detected.