Patents by Inventor Toshiyuki Usagawa

Toshiyuki Usagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10466198
    Abstract: In a gas sensor using a first FET-type sensor for a sensor unit, a gas density measurement unit measures a gas density of gas to be detected at a predetermined time on the basis of a first threshold change as a difference between a first threshold voltage applied to a first gate layer when a first source-drain current is a first threshold current while the gas to be detected is not present in the atmosphere and a second threshold voltage applied to the first gate layer when the first source-drain current is the first threshold current at the predetermined time while the gas to be detected is present in the atmosphere, and a temporal differentiation of the first threshold change.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 5, 2019
    Assignee: HITACHI, LTD.
    Inventors: Yoshitaka Sasago, Toshiyuki Usagawa, Hitoshi Nakamura
  • Patent number: 10151725
    Abstract: The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor. For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 11, 2018
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Kazuo Ono, Toshiyuki Usagawa
  • Publication number: 20180120253
    Abstract: In a gas sensor using a first FET-type sensor for a sensor unit, a gas density measurement unit measures a gas density of gas to be detected at a predetermined time on the basis of a first threshold change as a difference between a first threshold voltage applied to a first gate layer when a first source-drain current is a first threshold current while the gas to be detected is not present in the atmosphere and a second threshold voltage applied to the first gate layer when the first source-drain current is the first threshold current at the predetermined time while the gas to be detected is present in the atmosphere, and a temporal differentiation of the first threshold change.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 3, 2018
    Applicant: HITACHI, LTD.
    Inventors: Yoshitaka SASAGO, Toshiyuki USAGAWA, Hitoshi NAKAMURA
  • Patent number: 9857322
    Abstract: A semiconductor gas sensor includes a CMOS inverter which is configured by an n-channel field effect transistor having a catalytic gate and a p-channel field effect transistor having the catalytic gate. An input setting gate potential Vin(D) of the CMOS inverter is set to satisfy “Vin(D)=Vtc??Vgth” by using the sensor response threshold intensity ?Vgth determined by a concentration of a gas to be detected and a threshold input potential Vtc of the CMOS inverter. Therefore, only by setting the input setting gate potential Vin(D), a warning or an alarm can be issued for the concentration of the gas to be detected. In addition, a temperature compensation of the threshold voltage caused by a MOS structure is reduced regardless of the detection gas by setting a characteristic coefficient ?R, a threshold voltage Vtn of the n-channel field effect transistor, and the threshold voltage Vtp of the p-channel field effect transistor so as to satisfy relations “?R=1” and “Vtp=?Vtn”.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: January 2, 2018
    Assignee: HITACHI, LTD.
    Inventor: Toshiyuki Usagawa
  • Publication number: 20170370875
    Abstract: The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor. For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.
    Type: Application
    Filed: December 2, 2015
    Publication date: December 28, 2017
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Kazuo ONO, Toshiyuki USAGAWA
  • Patent number: 9484448
    Abstract: A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO2 film) is formed on a Si layer, and a modified TiOx (a TiOx nanocrystal) film is formed on the gate insulating film. Further, on the modified TiOx film, a Pt film is formed. This Pt film is composed of a plurality of Pt crystal grains, and in a crystal grain boundary gap existing among the plurality of Pt crystal grains, Ti and oxygen (O) are present, and particularly, a TiOx nanocrystal is formed on a surface in the vicinity of a grain boundary triple point as the center.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 1, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Toshiyuki Usagawa
  • Patent number: 9383329
    Abstract: The gas sensor has a substrate, a gate insulating film arranged on the substrate, and a gate electrode arranged on the gate insulating film, wherein the gate electrode comprises a metal oxide mixture film produced by mixing an oxygen-doped amorphous metal that contains oxygen with crystals of an oxide of the metal and a platinum film formed on the metal oxide mixture film, the platinum film is composed of multiple platinum crystal grains and grain boundary regions that are present between the platinum crystal grains, the grain boundary regions are filled with a metal oxide mixture, and each of the platinum crystal grains is surrounded by the metal oxide mixture.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: July 5, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Toshiyuki Usagawa
  • Publication number: 20160097731
    Abstract: A semiconductor gas sensor includes a CMOS inverter which is configured by an n-channel field effect transistor having a catalytic gate and a p-channel field effect transistor having the catalytic gate. An input setting gate potential Vin(D) of the CMOS inverter is set to satisfy “Vin(D)=Vtc??Vgth” by using the sensor response threshold intensity ?Vgth determined by a concentration of a gas to be detected and a threshold input potential Vtc of the CMOS inverter. Therefore, only by setting the input setting gate potential Vin(D), a warning or an alarm can be issued for the concentration of the gas to be detected. In addition, a temperature compensation of the threshold voltage caused by a MOS structure is reduced regardless of the detection gas by setting a characteristic coefficient ?R, a threshold voltage Vtn of the n-channel field effect transistor, and the threshold voltage Vtp of the p-channel field effect transistor so as to satisfy relations “?R=1” and “Vtp=?Vtn”.
    Type: Application
    Filed: May 23, 2013
    Publication date: April 7, 2016
    Applicant: HITACHI, LTD.
    Inventor: Toshiyuki USAGAWA
  • Patent number: 9228973
    Abstract: A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: January 5, 2016
    Assignee: HITACHI, LTD.
    Inventor: Toshiyuki Usagawa
  • Publication number: 20130313569
    Abstract: A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO2 film) is formed on a Si layer, and a modified TiOx (a TiOx nanocrystal) film is formed on the gate insulating film. Further, on the modified TiOx film, a Pt film is formed. This Pt film is composed of a plurality of Pt crystal grains, and in a crystal grain boundary gap existing among the plurality of Pt crystal grains, Ti and oxygen (O) are present, and particularly, a TiOx nanocrystal is formed on a surface in the vicinity of a grain boundary triple point as the center.
    Type: Application
    Filed: April 25, 2013
    Publication date: November 28, 2013
    Applicant: Hitachi, Ltd.
    Inventor: Toshiyuki USAGAWA
  • Publication number: 20130186178
    Abstract: The gas sensor has a substrate, a gate insulating film arranged on the substrate, and a gate electrode arranged on the gate insulating film, wherein the gate electrode comprises a metal oxide mixture film produced by mixing an oxygen-doped amorphous metal that contains oxygen with crystals of an oxide of the metal and a platinum film formed on the metal oxide mixture film, the platinum film is composed of multiple platinum crystal grains and grain boundary regions that are present between the platinum crystal grains, the grain boundary regions are filled with a metal oxide mixture, and each of the platinum crystal grains is surrounded by the metal oxide mixture.
    Type: Application
    Filed: August 9, 2011
    Publication date: July 25, 2013
    Applicant: HITACHI, LTD.
    Inventor: Toshiyuki Usagawa
  • Publication number: 20120217550
    Abstract: A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.
    Type: Application
    Filed: October 1, 2010
    Publication date: August 30, 2012
    Applicant: HITACHI, LTD.
    Inventor: Toshiyuki Usagawa
  • Patent number: 7541811
    Abstract: A compact, lightweight, and easy-to-use ESR-CT apparatus including a magnetic field leak line (5-G line) which is capable of imaging a small animal, such as a mouse, within 15 minutes, and of observing a desired region with a spatial resolution of 1 mm or less. A permanent magnet system is introduced of the apparatus includes pole pieces having a predetermined area which are opposed to each other through a measured space, yokes combined with the pole pieces, and a permanent magnet inserted in series so that at least one magnetic pole plane intersects perpendicularly to the closed magnetic circuit for magnetic coupling with the yokes. This makes it possible to locate a gradient coil system and a field scanning coil system sufficiently apart from end faces of the pole pieces, and to downsize the field scanning coil system so that the gradient field system is movable.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: June 2, 2009
    Assignee: Hitachi, Ltd.
    Inventor: Toshiyuki Usagawa
  • Publication number: 20080061782
    Abstract: The present invention provides a compact, lightweight, and easy-to-use ESR-CT apparatus including a magnetic field leak line (5-G line), the apparatus being capable of imaging a small animal, such as a mouse, within 15 minutes with a spatial resolution of 1 mm or less and observing a desired region with a spatial resolution of 1 mm or less. A permanent magnet system for magnetic space is introduced, the system comprising: pole pieces having a predetermined area which are opposed to each other through a space; yokes combined with the pole pieces; and a permanent magnet inserted in series in a closed magnetic circuit formed by the pole pieces, the yokes, and a space between the pole pieces so that a magnetic pole plane intersects perpendicularly to the closed magnetic circuit for magnetic coupling with the yokes.
    Type: Application
    Filed: July 6, 2007
    Publication date: March 13, 2008
    Inventor: TOSHIYUKI USAGAWA
  • Patent number: 5746826
    Abstract: Utilizing rugged pattern of atomic size present on a crystalline substrate of a semiconductor such as silicon or selenium or the like, a microstructure body is produced on the substrate by forming a layer of a first element of one monolayer or less by arranging at the position of the substrate most stable in energy formed by ruggedness the atoms of the first element such as gold, silver, copper, nickel, palladium, platinum or an element of group IV and then depositing successively atoms of at least one second element of group III, group IV and group V on only at a part of the surface of the substrate on which said layer of one monolayer or less by vapor deposition, sputtering or the like.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Hasegawa, Shigeyuki Hosoki, Makiko Kohno, Masakazu Ichikawa, Hitoshi Nakahara, Toshiyuki Usagawa
  • Patent number: 5670804
    Abstract: A semiconductor device is diclosed which has a PN-junction gate field effect transistor constituting a PN-junction gate with a semiconductor layer of opposite conductivity, an undoped semiconductor layer, and an active layer by depositing sources and drains made of semiconductor layers on the active layer of uniconductivity, depositing an undoped semiconductor layer whose band gap is greater than that of the active layer on the active layer between the opposing end surfaces of the sources and drains, and depositing a semiconductor layer of opposite conductivity on the undoped semiconductor layer away from the sources and drains. In particular, the present invention is effective for an enhancement type PN-junction power FET using compound semiconductors such as GaAs and capable of running with a single power supply and for a semi-conductor device integrating the enhancement type PN-junction power FET and a high-frequency low noise amplifier mono-lithically.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: September 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Akemi Sawada, Kenichi Tominaga
  • Patent number: 5567961
    Abstract: A semiconductor device may include a double hetero junction bipolar transistor and a field-effect transistor. The base of the bipolar transistor and the gate of the field-effect transistor are connected to each other to serve as an input terminal and the collector of the bipolar transistor and the drain of the field-effect transistor are connected to each other to serve as an output terminal. The bipolar transistor and the field-effect transistor may be created on a common substrate. In this case, both the bipolar and field-effect transistors can have the same multilayer/film structures.
    Type: Grant
    Filed: August 3, 1993
    Date of Patent: October 22, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Atsushi Takai, Hiroyuki Itoh
  • Patent number: 5455451
    Abstract: Superconductized electronic devices, such as a Josephson junction device, or superconductized optical devices represented by a light emitting and receiving devices of semiconductor laser are available using semiconductor materials which normally have no superconducting characteristics. The devices can operate by controlling the behavior of a Cooper pair in an active region which is formed in the semiconductor in advance using the penetrating phenomenon of the Cooper pair caused in the semiconductor proximate to the superconductor.
    Type: Grant
    Filed: April 22, 1993
    Date of Patent: October 3, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Masashi Kawasaki, Kensuke Ogawa, Toshiyuki Aida
  • Patent number: 5381027
    Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: January 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Kenji Hiruma, Masahiko Kawata, Shigeo Goto, Katsuhiko Mitani, Masao Yamane, Susumu Takahashi, Tomonori Tanoue, Yoshinori Imamura
  • Patent number: 5373191
    Abstract: Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: December 13, 1994
    Assignee: Hitachi Ltd.
    Inventors: Toshiyuki Usagawa, Yoshinori Imamura, Hidekazu Okuhira, Shigeo Goto, Masayoshi Kobayashi, Shinichiro Takatani