Abstract: An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.

Abstract: A microprocessor having a register bank architecture has n register banks, a memory, a bus for connecting the register bank and the memory, and a bank controller for controlling store/load operations between the register banks and the memory. The controller has a current bank pointer indicating data region of the register banks and the memory during the data store/load operations, and a bank size designation register indicating a bank size to be stored/loaded during the store/load operations. When an address of the current bank pointer is set in an destination operand in an instruction, the controller receives the contents of the current bank pointer and bank size designation register.

Abstract: A data communication control device controls data transmission between a network bus and a system bus. The data communication control device includes a network bus interface connected to the network bus, a system bus interface connected to the system bus. A port 1 of the two-port memory in an FIFo/RAM is connected to the network bus interface, microprocessor, direct memory access through a first bus. A port 2 of the two-port memory in the FIFo/RAM is connected to the direct memory access through a second bus. The microprocessor is connected to the system bus interface through a third bus. The direct memory access is connected to the system bus interface through a fourth bus.

Abstract: An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, includes: many scan register groups obtained by dividing many F/Fs provided in each functional block, many scan paths for scanning a plurality of test data used for input and output operations for the scan register groups, wherein a scan path is provided for each scan register group, and a decoder for designating the scan paths and controlling the input and output operations of test signals used for testing the scan register groups. A first scan register group in each functional group is composed of scan registers only used for the input operations to other functional blocks, a second scan register group is composed of scan registers only used for the output operations to other functional blocks and a third scan register group is composed of scan registers used for the input and output operations to the same functional block.

Abstract: Disclosed is a test facilitating circuit which is incorporated in an LSI system having a plurality of master modules and a plurality of slave modules, a common bus for connecting the master modules and the slave modules, and a bus arbiter for adjusting use of the common bus. The test circuit utilizes tri-state buffers and control lines for prohibiting transmission of an acknowledgement signal from the bus arbiter to a master module to be tested among the plurality of master modules in a test mode. The test circuit inputs an acknowledgement signal generated from the master module, and which outputs it to the slave modules. An AND gate is used for masking acknowledgement signals to be transmitted from the bus arbiter to master modules other than the master module to be tested.

Abstract: An evaluation facilitating circuit is for selectively evaluating each of block of a logical circuit to be checked which is divided into the plurality of blocks. The evaluation facilitating circuit includes a data hold circuit for selectively latching level signals of nodes of each of blocks and a data hold and transfer control circuit for controlling the data hold circuit.

Abstract: A logic circuit which can easily perform a logical function test is disclosed. A first type of the logic circuit comprises a combinational circuit having a plurality of internal nodes, node data latch circuits respectively connected to the preselected internal nodes for latching their logical states, and readout means for reading data latched in the latch circuits by using a data transfer clock. Further, there may be adopted implementation such that the node data latch circuit functions to allow a predetermined node to be placed in the logical state latched in the node data latch circuit. Thus, this first type of the logic circuit makes it possible to monitor even logical states of internal nodes of the combinational circuit. A second type of the logic circuit comprises a combinational circuits, a plurality of memory means, designation means e.g.

Abstract: In floating-point multiplication, the sum of the exponents of the two operands is determined by the use of a single adder. The exponents are modified either before they are inputted to the adder or at the output of the adder. A carry signal of "1" is applied whenever addition is carried out. A signal indicative of occurrence of underflow or overflow is also obtained.

Abstract: An apparatus for manufacturing from a cassette which initially has a continuous leader extending between and connected to a pair of rotary hubs thereof and from an elongated flexible information material carrying information which can be extracted from the material a cassette which has a length of the information material stored in the cassette with opposed ends of the information material connected with leaders which are respectively connected to the rotary hubs of the cassette.