Patents by Inventor Toshiyuki Yokoe

Toshiyuki Yokoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8581378
    Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano
  • Patent number: 8378468
    Abstract: By increasing the area of a source electrode 3a of a semiconductor element 3 and the area of a source terminal 2b of a lead frame 2, it is possible to extend a joint 8a of the source electrode 3a bonded to a conductive ribbon 6 and a joint 8b of the source terminal 2b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: February 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Patent number: 8378467
    Abstract: Retaining regions 310a and 310b are added to a pad shaped portion 303a of leads and a die pad 302 that are electrically connected via a conductive ribbon 309, so that during the bonding of the ribbon, strong ultrasonic waves can be applied in a state in which the retaining regions 310a and 310b are pressed and fixed. It is therefore possible to reduce a resistance at a joint while firmly bonding the conductive ribbon 309. Further, the bonding strength of the conductive ribbon 309 increases and thus it is possible to eliminate the need for stacking the conductive ribbons 309 and easily reduce a stress caused by ultrasonic waves on a semiconductor chip 306.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Publication number: 20110163431
    Abstract: Retaining regions 310a and 310b are added to a pad shaped portion 303a of leads and a die pad 302 that are electrically connected via a conductive ribbon 309, so that during the bonding of the ribbon, strong ultrasonic waves can be applied in a state in which the retaining regions 310a and 310b are pressed and fixed. It is therefore possible to reduce a resistance at a joint while firmly bonding the conductive ribbon 309. Further, the bonding strength of the conductive ribbon 309 increases and thus it is possible to eliminate the need for stacking the conductive ribbons 309 and easily reduce a stress caused by ultrasonic waves on a semiconductor chip 306.
    Type: Application
    Filed: September 8, 2009
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Publication number: 20110163392
    Abstract: By increasing the area of a source electrode 3a of a semiconductor element 3 and the area of a source terminal 2b of a lead frame 2, it is possible to extend a joint 8a of the source electrode 3a bonded to a conductive ribbon 6 and a joint 8b of the source terminal 2b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Chie Fujioka, Toshiyuki Yokoe, Daichi Kumano
  • Publication number: 20110115062
    Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.
    Type: Application
    Filed: September 29, 2009
    Publication date: May 19, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano