Abstract: A PLL circuit comprising a phase comparator unit which forms a differentiation signal based upon both edges of an external signal, outputs an early pulse only during a period in which the differentiation signal is overlapped on a period from the leading edge to the trailing edge of a reference signal, and outputs a late pulse only during a period in which the differentiation signal is overlapped on a period from the trailing edge to the leading edge thereof, a charge pump unit which calculates and compares the amounts of integration of the early pulse and the late pulse, lowers the output voltage when the amount of the late pulse is larger than the amount of the early pulse and raises the output voltage when it is smaller, and a VCO which outputs a corrected reference signal of which the frequency decreases or increases accompanying the increase or decrease in the output voltage of the charge pump unit, wherein the VCO is controlled by the output voltage of the charge pump unit and by the early pulse and the

Abstract: A charge-pump circuit for controlling a voltage controlled oscillator by converting a phase difference between two input signals, which never become low at the same time, into a voltage. The charge-pump circuit includes first and second feeder circuits, made of bipolar transistors, outputting current in accordance with the input signals; a capacitor circuit having first, second, and third capacitors, and the first and the second or the first and the third capacitors are charged by the output current from the first or the second feeder circuit; and a differential amplifying circuit amplifying the voltage between the ends of the first capacitor to a predetermined voltage for output. The differential amplifying circuit operates to draw the same leakage current from the second and the third capacitors when the first capacitor is not being charged.

Abstract: A waveform synthesizing circuit comprises a plurality of signal output switching means for outputting predetermined magnitudes of voltage or current signals when a voltage or current value of an input pulse reaches preliminarily assigned comparing reference values, a signal summing means for superimposing output signals from a plurality of signal output switching means for summing, and a comparing signal switching means detecting the rising and falling of the input pulse, providing the comparing reference values with given differences between a plurality of signal output switching means according to an order of operation of a plurality of signal output switching means upon the detection of a rise, and providing the comparing reference values, which are different from those for rising, with given differences between a plurality of signal output switching means according to an order of operation of a plurality of signal output switching means upon the detection of a fall.