Patents by Inventor Tou-Sung Wu

Tou-Sung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040183179
    Abstract: A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and th
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Chia-Chieh Hu, Ning Huang, Hui-Pin Chen, Chang-Ming Hsin, Shu-Wan Lu, Tou-Sung Wu, Chih-Yu Tsai, Yu-Tang Su, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang
  • Publication number: 20030160316
    Abstract: An open-typed multi-chip stack-packaging is disclosed and the packaging comprises a substrate having a first surface and a second surface, at least a through opening formed on the substrate, and including at least two layers of circuitry to electrically transmit signals; at least a first chip positioned on the upper section of the opening of the first surface and a plurality of protruded blocks being soldered onto the circuitry on the first surface of the substrate at the external region of the substrate for electrically connection; at least a second chip stacked onto the first chip and the second chip being connected electrically to the circuitry of the first surface with gold lines; at least a third chip positioned at the lower section of the opening of the second surface and having a size smaller than the first chip, and a plurality of protruded blocks being used to electrically bond with the center position of the first chip, and adhesive being used to fill the first chip and the third chip, and the regio
    Type: Application
    Filed: January 13, 2003
    Publication date: August 28, 2003
    Inventors: Wen-Lo Shieh, Fu-Yu Huang, Ning Huang, Hui-Pin Chen, Shu-Wan Lu, Tou-Sung Wu, Chih-Yu Tsai, Mei-Hua Chen, Chia-Ling Lu, Yu-Ju Wang