Patents by Inventor Tousaku Nakanishi

Tousaku Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4404545
    Abstract: Errors in determining a measured voltage are mathematically canceled in an analog-to-digital converter circuit useful for dual slope type using positive and negative values of a reference voltage. The errors are due to the off-set voltages inherent to operational amplifiers employed for an integrator and a comparator included within the analog-to-digital converter circuit. A counter circuit is provided for storing time information related to first and second dual slopes. A mathematical calculation is conducted with the aid of all the time information of the first and second dual slopes, whereby the measured voltage can be determined with eliminating the influence by the off-set voltage.
    Type: Grant
    Filed: April 28, 1981
    Date of Patent: September 13, 1983
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tousaku Nakanishi, Hiroshi Tsuda
  • Patent number: 4237803
    Abstract: A read only memory (ROM) is provided for storing digital information related to stitch patterns and control instructions for stitch formation purposes. A keyboard means is provided for selecting a desired stitch pattern and control instruction stored in the ROM. Selected digital information is introduced into a random access memory (RAM) and temporarily stored therein. The RAM develops control signals for controlling the needle position and the work feed in accordance with the control instruction selected through the keyboard means.
    Type: Grant
    Filed: October 19, 1977
    Date of Patent: December 9, 1980
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tousaku Nakanishi, Kazuo Suzuki, Masayasu Makino, Nobuyoshi Miyao, Hirokazu Koda