Patents by Inventor Toyoaki Sakai
Toyoaki Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818847Abstract: A resist layer forming method includes a process of laminating a resist layer on a base at a first pressure using a laminate roller having a first temperature, and a process of pressing the resist layer against the base at a second pressure higher than the first pressure using a metal plate having a second temperature lower than the first temperature.Type: GrantFiled: April 5, 2022Date of Patent: November 14, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yoshihisa Kanbe, Toyoaki Sakai
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Publication number: 20230009751Abstract: A wiring board includes a base material, a through hole that is formed in the base material, a magnetic member that is embedded in the through hole, and a plating film that covers end faces of the magnetic member exposed from the through hole. The magnetic member includes a conductor wire that is covered by a magnetic body. A wiring board manufacturing method includes forming a through hole in a base material, forming a magnetic member by covering a conductor wire by a magnetic body, embedding the magnetic member in the through hole, and forming a plating film that covers end faces of the magnetic member exposed from the through hole.Type: ApplicationFiled: July 6, 2022Publication date: January 12, 2023Inventors: Toshiaki Aoki, Toyoaki Sakai
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Publication number: 20220338354Abstract: A resist layer forming method includes a process of laminating a resist layer on a base at a first pressure using a laminate roller having a first temperature, and a process of pressing the resist layer against the base at a second pressure higher than the first pressure using a metal plate having a second temperature lower than the first temperature.Type: ApplicationFiled: April 5, 2022Publication date: October 20, 2022Inventors: Yoshihisa KANBE, Toyoaki SAKAI
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Patent number: 10170405Abstract: A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.Type: GrantFiled: July 10, 2017Date of Patent: January 1, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Toyoaki Sakai
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Patent number: 9911695Abstract: A wiring board includes an insulating layer, a first wiring layer, and a second wiring layer. The first wiring layer is formed in a first surface of the insulating layer, and includes a pad on which a semiconductor chip is to be mounted and a wiring pattern. The second wiring layer is formed on a second surface of the insulating layer opposite to the first surface. The roughness of a surface of the first wiring layer exposed at the first surface of the insulating layer is smaller than the roughness of a surface of the second wiring layer exposed on the second surface of the insulating layer.Type: GrantFiled: August 23, 2016Date of Patent: March 6, 2018Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Toyoaki Sakai
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Publication number: 20180019196Abstract: A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.Type: ApplicationFiled: July 10, 2017Publication date: January 18, 2018Inventor: Toyoaki SAKAI
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Patent number: 9699912Abstract: A wiring board includes an insulating layer; and a wiring layer embedded in the insulating layer at one surface side of the insulating layer, one surface of the wiring layer being exposed from one surface of the insulating layer, the wiring layer including a first portion and a second portion whose width is wider than that of the first portion, one surface of the first portion and one surface of the second portion being flush with each other, and the first portion being thinner than the second portion.Type: GrantFiled: April 13, 2016Date of Patent: July 4, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Toyoaki Sakai, Tomoyuki Shimodaira, Shunichiro Matsumoto, Kentaro Kaneko
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Publication number: 20170098600Abstract: A wiring board includes an insulating layer, a first wiring layer, and a second wiring layer. The first wiring layer is formed in a first surface of the insulating layer, and includes a pad on which a semiconductor chip is to be mounted and a wiring pattern. The second wiring layer is formed on a second surface of the insulating layer opposite to the first surface. The roughness of a surface of the first wiring layer exposed at the first surface of the insulating layer is smaller than the roughness of a surface of the second wiring layer exposed on the second surface of the insulating layer.Type: ApplicationFiled: August 23, 2016Publication date: April 6, 2017Inventor: Toyoaki SAKAI
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Publication number: 20160316560Abstract: A wiring board includes an insulating layer; and a wiring layer embedded in the insulating layer at one surface side of the insulating layer, one surface of the wiring layer being exposed from one surface of the insulating layer, the wiring layer including a first portion and a second portion whose width is wider than that of the first portion, one surface of the first portion and one surface of the second portion being flush with each other, and the first portion being thinner than the second portion.Type: ApplicationFiled: April 13, 2016Publication date: October 27, 2016Inventors: Toyoaki SAKAI, Tomoyuki SHIMODAIRA, Shunichiro MATSUMOTO, Kentaro KANEKO
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Patent number: 8143533Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.Type: GrantFiled: May 17, 2006Date of Patent: March 27, 2012Assignees: Mitsubishi Paper Mills Limited, Shinko Electric Industries Co., Ltd.Inventors: Yasuo Kaneda, Munetoshi Irisawa, Yuji Toyoda, Toyokazu Komuro, Katsuya Fukase, Toyoaki Sakai
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Patent number: 7679004Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on thType: GrantFiled: March 2, 2005Date of Patent: March 16, 2010Assignees: Shinko Electric Industries Co., Ltd., Mitsubishi Paper Mills LimitedInventors: Katsuya Fukase, Toyoaki Sakai, Munetoshi Irisawa, Toyokazu Komuro, Yasuo Kaneda, Masanori Natsuka, Wakana Aizawa
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Publication number: 20090236137Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.Type: ApplicationFiled: May 17, 2006Publication date: September 24, 2009Inventors: Yasuo Kaneda, Munetoshi Irisawa, Yuji Toyoda, Toyokazu Komuro, Katsuya Fukase, Toyoaki Sakai
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Patent number: 7454832Abstract: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).Type: GrantFiled: August 18, 2006Date of Patent: November 25, 2008Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toyoaki Sakai, Katsuya Fukase
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Publication number: 20080197294Abstract: An exposure method includes: (a) providing a substrate coated with a photosensitive material on a stage; and (b) applying a spot light beam emitted from a light source to the photosensitive material while moving the stage in accordance with a previously programmed exposure pattern for wiring formation, thereby performing pattern exposure of the photosensitive material. In the exposure method, the spot light beam is controlled so that the spot light beam is formed into an ellipse whose major axis is in a direction perpendicular to a move direction of the stage.Type: ApplicationFiled: February 13, 2008Publication date: August 21, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Toyoaki SAKAI
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Publication number: 20070181994Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on thType: ApplicationFiled: March 2, 2005Publication date: August 9, 2007Applicants: SHINKO ELECTRIC INDUSTRIES CO., LTD., MITSUBISHI PAPER MILLS LIMITEDInventors: Katsuya Fukase, Toyoaki Sakai, Munetoshi Irisawa, Toyokazu Komuro, Yasuo Kaneda, Masanori Natsuka, Wakana Aizawa
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Publication number: 20070042585Abstract: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).Type: ApplicationFiled: August 18, 2006Publication date: February 22, 2007Inventors: Toyoaki Sakai, Katsuya Fukase
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Publication number: 20070017090Abstract: A method of forming a high aspect ratio metal plate pattern and a circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one of two surfaces of a copper plate (10) and patterned to form a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is selectively half etched. By coating, exposing and developing the positive resist (18), the side etched portion under the tin plating layer is protected by the positive resist. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a mask are finally removed to produce a metal pattern (20).Type: ApplicationFiled: July 13, 2006Publication date: January 25, 2007Inventors: Toyoaki Sakai, Katsuya Fukase
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Patent number: 7005241Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.Type: GrantFiled: April 13, 2004Date of Patent: February 28, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Katsuya Fukase, Toyoaki Sakai
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Publication number: 20050124091Abstract: A process for forming a metal pattern comprising the following steps of: (a) half-etching a metal plate from one or respective sides thereof by means of first masking which is positioned on one or respective surfaces of the metal plate; (b) applying positive liquid resist on the half-etched metal plate from one or respective sides of the first masking; (c) exposing the positive liquid resist with light from one or respective sides of the first masking; (d) developing the positive liquid resist in such a manner that unexposed positive liquid resist located under the first masking is protected and exposed, uncured liquid resist is removed; (e) half-etching again the metal plate from one or respective sides thereof by means of second masking composed of the first masking and the protected positive liquid resist; (f) repeating the steps (b) to (e) until a metal pattern is obtained from the metal plate; and (g) removing the first masking, and the second or subsequent masking of the unexposed positive liquid resistType: ApplicationFiled: November 2, 2004Publication date: June 9, 2005Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Katsuya Fukase, Toyoaki Sakai
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Publication number: 20040245213Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.Type: ApplicationFiled: April 13, 2004Publication date: December 9, 2004Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Katsuya Fukase, Toyoaki Sakai