Abstract: A coprocessor system is disclosed in which a CPU in a game machine body and a CPU in a game cartridge are formed by CPU cores having the same architecture and memory mapping functions. The cycle time of a second CPU, for example the CPU in the game cartridge, is shorter than the cycle time of the first CPU, for example the CPU in the game machine body. The first CPU accesses memory during a first time period that is longer than the program memory access time but shorter than the first CPU cycle time. The second CPU accesses the program memory during a second time period, which is the time difference between the end of the first time period and the end of the first CPU's cycle time. The second CPU may also access the program memory during the first time period if no first CPU memory access is pending. Since the first CPU's memory access during the first time period has priority over the second CPU's, the first CPU never waits to access shared memory.

Abstract: A variable bit-length code processing circuit includes first, second and third registers (12, 20, 22) each of which is of 1 word, and memory data is loaded to the first register (12), and a variable bit-length code is withdrawn from the third register (22). The second register (20) and third register (22) are coupled to a barrel shifter (16) which barrel-shifts data of 2 words according to a barrel shift amount which is applied by a subtracter (30) on the basis of the number of the valid bits and the number of the remaining bits.

Abstract: A video display apparatus includes a video data generator which generates video data of a plurality of still picture and a moving picture (graphic data) in an overlaid manner on the basis of still picture patterns, still picture character codes, moving picture character codes and etc. programmed in an external storage unit in advance. A microprocessor applies, in accordance with priority data for the still pictures and the moving picture and mode data both programmed in the external storage unit in advance, first priority data to the video data of the still picture characters and second priority data to the video data of the moving picture character, respectively. A priority encoder selects a still picture character or a moving picture character having the highest priority on the basis of the first and second priority data, and applies the number of that character to a decoder. The decoder outputs a gate control signal in accordance with the number.

Abstract: A moving picture display apparatus comprises a main body and an external memory detachably mounted on the main body. The main body of the moving picture display apparatus is provided with a video data memory for storing therein graphic data of characters which constitute objects. A program data memory of the external memory has object data of an object to be displayed on a raster-scan type monitor, i.e., color pallet data, object name data, vertical position data, horizontal position data, object size selection data and size designation data and etc., all of which have previously been stored therein. Object data of an object to be displayed during the next vertical period is read from the program data memory so as to be stored in an object attribute memory.

Abstract: A display range control apparatus includes an external storage unit in which position data representative of two points in a horizontal direction on a screen of a raster scan monitor are stored in advance together with still picture pattern data and character data. A counter is incremented for each dot or pixel on the screen. In a range where each of the position data is coincident with a count value of the counter, a masking signal is obtained. The masking signal is used for gating picture data using a gate circuit. The picture data outputted from the gate circuit is converted into a video signal which is then applied to the monitor.

Abstract: An image processing apparatus includes a CPU which executes a program read from an external storage unit, and a video processor. In the video processor, color data of moving picture characters and color data of still picture characters are respectively outputted from a moving picture data generating circuit and a still picture data generating circuit. Both the color data are applied to a main/subsidiary data selection circuit which outputs the color data as main image data and subsidiary image data. An arithmetic circuit executes an arithmetic operation to obtain a mean value of both the color data. A video signal producing circuit converts the mean value of the color data from the arithmetic circuit into a video signal which is then applied to a display.

Abstract: A still picture display apparatus displays a still picture in which characters each composed of combination of a predetermined number of dots on a raster scan monitor in accordance with character data and program data both stored in an external storage device in advance. Offset data of at least one of a horizontal direction and a vertical direction correspondingly to each character is stored in an offset table formed in the external storage device. A picture processing unit determines an address on the basis of the offset data and at least one of a horizontal position and a vertical position, and reads video data from a video data memory according to the address to apply to the raster scan monitor.

Abstract: A background picture display apparatus includes a microprocessor and an external storage unit, and dot data, character designating data and mode data are programmed in advance in a ROM in the external storage unit. Character designating data constituting background screens designated by the mode data and dot data of the respective characters used in the background screens are loaded in a RAM, that is, a screen RAM and a character RAM by a microprocessor. The character designating data is read from the screen RAM, and the dot data of the character is read from the character RAM. The dot data is converted into serial data by a parallel-serial conversion circuit, and a dot data combination circuit generates a color code for each background screen by combining the dot data and applies the same to a color generation circuit.

Abstract: A mosaic picture display apparatus includes a picture processing unit and an external storage unit connected thereto. Mosaic size data is programmed in the external storage unit. In response to a control signal which is generated for each mosaic having a mosaic size determined by the mosaic size data at timing of the start thereof, a latch latches still picture character data outputted from a register. Therefore, each of dots in the mosaic is displayed by the same latched character data.

Abstract: A background picture display apparatus includes a microprocessor and an external storage unit, and dot data, character designating data and mode data are programmed in advance in a ROM in the external storage unit. Character designating data constituting background screens designated by the mode data and dot data of the respective characters used in the background screens are loaded in a RAM, that is, a screen RAM and a character RAM by a microprocessor. The character designating data is read from the screen RAM, and the dot data of the character is read from the character RAM. The dot data is converted into serial data by a parallel-serial conversion circuit, and a dot data combination circuit generates a color code for each background screen by combining the dot data and applies the same to a color generation circuit.

Abstract: A still picture display apparatus displays a still picture in which characters each composed of combination of a predetermined number of dots on a raster scan monitor in accordance with character data and program data both stored in an external storage device in advance. Offset data of at least one of a horizontal direction and a vertical direction correspondingly to each character is stored in an offset table formed in the external storage device. A picture processing unit determines an address on the basis of the offset data and at least one of a horizontal position and a vertical position, and reads video data from a video data memory according to the address to apply to the raster scan monitor.

Abstract: A video processing apparatus includes a VRAM in which image data of an original background picture is stored. An address of the VRAM in a case where the original background picture is rotated and enlarged or reduced is calculated by a background picture address control circuit on the basis of constants set by a CPU. Color data of the background picture at the time of rotation processing and enlargement or reduction processing is read from the address of the VRAM, and a video signal is generated by the color data.

Abstract: A direct memory access apparatus includes a CPU, and data of one byte or more to be transferred is stored in a working RAM of the CPU or an external storage unit. The external storage unit includes a memory cartridge or a CD-ROM, and stores parameter data including the number of data to be transferred, and a first address and second address for direct memory access. Prior to a start of the direct memory access, the parameter data is read and, when a horizontal blanking signal is generated from a counter included in a video processor, the data is read from the working RAM or the external storage unit in accordance with the first address value and the data is transferred to an internal memory of the video processor in accordance with the second address value.

Abstract: A voltage level converting circuit for use in semiconductor devices including memory such as ROMs, PROMs and EPROMs comprises an input terminal to which an input signal is applied, a voltage level detecting circuit for detecting the voltage level of the input signal received by the input terminal and supplying an output signal of the voltage level determined in response to the level of the input signal, an inverter connected to the voltage level detecting circuit and a CMOS device having a pair of outside source/drain terminals connected between the input terminal and a first reference voltage, a gate terminal connected to the output of the inverter and the inner interconnected source/drain terminals connected to an output terminal of the circuit.