Patents by Inventor Toyohiko Kumakura

Toyohiko Kumakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6855893
    Abstract: A wiring board includes a predetermined wiring section disposed on an insulation board, and an electromagnetic shielding film is placed at a position close to the wiring section. A semiconductor device includes an electromagnetic shielding film disposed on a surface, on which an integrated circuit of a semiconductor chip has been formed, through an insulative film, a lead is provided on the electromagnetic shielding film through an insulative film, the lead is electrically connected to an external terminal of the semiconductor chip, and the resulting structured material is sealed with a sealing material; and a circuit board for electronic parts composed of a circuit board prepared by forming a plurality of leads on an insulating material, and a conductor disposed on the plurality of leads through an insulating material and reducing a self inductance of the plurality of leads by flowing an eddy current through the conductor.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: February 15, 2005
    Assignee: Hitachi Cable Ltd.
    Inventors: Toyohiko Kumakura, Gen Murakami, Tomo Yasuda, Masahiko Kobayashi, Hidetoshi Murakami
  • Publication number: 20040211591
    Abstract: There are provided a wiring board, wherein a predetermined wiring section is disposed on an insulation board, and an electromagnetic shielding film is placed at a position close to the wiring section; a semiconductor device, wherein an electromagnetic shielding film is disposed on a surface, on which an integrated circuit of a semiconductor chip has been formed, through an insulative film, a lead is provided on the electromagnetic shielding film through an insulative film, the lead is electrically connected to an external terminal of the semiconductor chip, and the resulting structured material is sealed with a sealing material; and a circuit board for electronic parts composed of a circuit board prepared by forming a plurality of leads on an insulating material, and a conductor disposed on the plurality of leads through an insulating material and reducing a self inductance of the plurality of leads by flowing an eddy current through the conductor.
    Type: Application
    Filed: November 27, 2002
    Publication date: October 28, 2004
    Applicant: HITACHI CABLE LTD.
    Inventors: Toyohiko Kumakura, Gen Murakami, Tomo Yasuda, Masahiko Kobayashi, Hidetoshi Murakami
  • Patent number: 6114751
    Abstract: It is an object of the invention to reduce noise superposed on a driving voltage of a semiconductor device and a clock signal on a transmission line. It is a further object of the invention to equalize transmission distances of signal lines in a transmission line provided between the semiconductor devices. It is a still further object of the invention to provide a electronic device, which composed of a microprocessor unit, a semiconductor device--controlling equipment and plural semiconductor devices according to the invention, each being mounted on a printed circuit board having plural bus channel lines with an equal transmission distance. In the semiconductor device of LOC structure, the leads in the outside of the package positioned at the left side and those at the right side are shifted from each other by a half pitch of the leads. A metallic film for shielding a semiconductor chip from electromagnetic wave is set close to leads.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: September 5, 2000
    Assignee: Hitachi Cable, Ltd.
    Inventors: Toyohiko Kumakura, Gen Murakami, Tomo Yasuda
  • Patent number: 6031292
    Abstract: A substrate 1 of a insulating resin material is provided with a semiconductor chip 2 in the center of the substrate 1 and a lot of fine studs are filled in the substrate 1 around the chip 2. A bonding pad 13 and a land 14 are formed on both end planes of each stud 12 by silver plating. The length of the stud 12 is determined so that the plane of the land 14 and the back side plane of the substrate are approximately co-planar, but it may be longer. The substrate 1 including the studs 12 having the bonding pad 12 and the land 14 is defined as an interposer 15.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: February 29, 2000
    Assignee: Hitachi Cable, Ltd.
    Inventors: Gen Murakami, Mamoru Mita, Toyohiko Kumakura, Norio Okabe, Katsuji Komatsu, Shoji Shinzawa
  • Patent number: 5866948
    Abstract: A substrate 1 of a insulating resin material is provided with a semiconductor chip 2 in the center of the substrate 1 and a lot of fine studs are filled in the substrate 1 around the chip 2. A bonding pad 13 and a land 14 are formed on both end planes of each stud 12 by silver plating. The length of the stud 12 is determined so that the plane of the land 14 and the back side plane of the substrate are approximately co-planar, but it may be longer. The substrate 1 including the studs 12 having the bonding pad 12 and the land 14 is defined as an interposer 15.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: February 2, 1999
    Assignee: Hitachi Cable, Ltd.
    Inventors: Gen Murakami, Mamoru Mita, Toyohiko Kumakura, Norio Okabe, Katsuji Komatsu, Shoji Shinzawa