Patents by Inventor Toyohiko Kuno

Toyohiko Kuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8551857
    Abstract: The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 8, 2013
    Assignees: Hitachi, Ltd., Asahi Kasei Microdevices Corporation
    Inventors: Yuji Imamura, Tsuyoshi Fujiwara, Toyohiko Kuno
  • Publication number: 20110210422
    Abstract: The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Inventors: Yuji IMAMURA, Tsuyoshi Fujiwara, Toyohiko Kuno
  • Patent number: 6541379
    Abstract: Grooves and holes of high aspect ratio are filled completely and uniformly. After forming connection holes (3) and wiring grooves (4) in a silicon oxide film (2) which is formed on a silicon substrate (1), a TiN film (5) is formed over the entire surface of the semiconductor substrate and a Ti film (6) is formed on the region except for the connection holes (3) and the wiring grooves (4). Then, in a state where the connection holes (3) and the wiring groove (4) are dipped in a plating solution, a plating treatment is carried out under a deposition overvoltage higher than the deposition overvoltage of TiN to copper and lower than the deposition overvoltage of Ti to copper.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 1, 2003
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Shoichiro Tonomura, Toyohiko Kuno
  • Publication number: 20020105090
    Abstract: Grooves and holes of high aspect ratio are filled completely and uniformly. After forming connection holes (3) and wiring grooves (4) in a silicon oxide film (2) which is formed on a silicon substrate (1), a TiN film (5) is formed over the entire surface of the semiconductor substrate and a Ti film (6) is formed on the region except for the connection holes (3) and the wiring grooves (4). Then, in a state where the connection holes (3) and the wiring groove (4) are dipped in a plating solution, a plating treatment is carried out under a deposition overvoltage higher than the deposition overvoltage of TiN to copper and lower than the deposition overvoltage of Ti to copper.
    Type: Application
    Filed: April 4, 2002
    Publication date: August 8, 2002
    Applicant: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Shoichiro Tonomura, Toyohiko Kuno
  • Patent number: 6384484
    Abstract: Grooves and holes of high aspect ratio are filled completely and uniformly. After forming connection holes (3) and wiring grooves (4) in a silicon oxide film (2) which is formed on a silicon substrate (1), a TiN film (5) is formed over the entire surface of the semiconductor substrate and a Ti film (6) is formed on the region except for the connection holes (3) and the wiring grooves (4). Then, in a state where the connection holes (3) and the wiring groove (4) are dipped in a plating solution, a plating treatment is carried out under a deposition overvoltage higher than the deposition overvoltage of TiN to copper and lower than the deposition overvoltage of Ti to copper.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: May 7, 2002
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Shoichiro Tonomura, Toyohiko Kuno
  • Patent number: 6162729
    Abstract: A method of forming a wiring of an aluminum material having a low-temperature sputtering process for sputtering an aluminum material (aluminum or an alloy composed mainly of aluminum) at a temperature of below 300.degree. C. and a high-temperature sputtering process for sputtering at or above 300.degree. C., a film thickness (A) obtained by the low-temperature sputtering process is larger than a film thickness (B) obtained by the high-temperature sputtering process, and a deposition rate at high temperature sputtering is a rate which does not deteriorate the shape of a registration accuracy measurement mark, preferably 200 nm/min or less.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 19, 2000
    Assignee: Asahi Kasei Kogyo Kabushiki Kaisha
    Inventors: Toyohiko Kuno, Kenichi Kitamura, Ken Tanaka
  • Patent number: 5330770
    Abstract: A water-soluble glass treating agent consisting essentially of, by weight: 55 to 80% of SiO.sub.2, 19.5 to 42% of Na.sub.2 O and 0.5 to 3% of Ag.sub.2 O (conversion for AgNO.sub.3) is disclosed. Also disclosed is a water-soluble glass treating agent further containing, by weight: 0.5 to 30% of Al.sub.2 O.sub.3 in the above compositions. These glass water treating agents are glass free from boron constituent but which functions to kill or suppress bacteria and micro-organisms and are low in cost because it is simple in the composition of glass which is composed principally of three constituents at max. That agent which contains Al.sub.2 O.sub.3 functions to increase concentration of Ag in glass and to decrease the deliquescent property of glass.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: July 19, 1994
    Assignee: Kinki Pipe Giken Kabushiki Kaisha
    Inventor: Toyohiko Kuno
  • Patent number: 4902432
    Abstract: A treating method of preventing the putrefaction and emission of rancidity of water-contained cutting or grinding oil by placing in the oil a treating bag member wherein solids comprised of water-soluble glass composition containing Ag.sup.30 ion in the composition thereof are wrapped in water-permeable fiber cloth. The method makes it possible to suppress the development of microbes forming which cause the putrefaction and rancidity of oil by the action of Ag.sup.30 ion so as to prolong the service period of the oil by a substantial degree and also to stabilize the effect by making Ag.sup.30 ion flow out in generally constant relation with lapse of time.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: February 20, 1990
    Assignee: Kinki Pipe Giken Kabushiki Kaisha
    Inventor: Toyohiko Kuno