Abstract: A register address specifying circuit capable of, besides accessing a register whose address is specified address, accessing also a register whose register address which is one address different from the specified register address, when executing the instruction for transferring a plurality of register contents, and a data processor which is able to access and transfer two register contents at the same time by comprising the same.

Abstract: A data processor wherein, in the case where an instruction decoder has decoded a multi-data transfer (storing or loading) instruction, bits in a register list outputted from the instruction decoder are searched by first and second priority encoders to encode respectively a position of "1" (or "0") and a position where "1" (or "0") is continued in two bits as binary digits, and when the encoded results do not coincide only one register corresponding to a bit position of the single "1" (or "0") is accessed, when the encoded results coincide the registers corresponding to the bit positions of the two continuous "1" (or "0") are accessed at the same time to process the multi-data transfer instruction effectively.

Abstract: A data processor which comprises: an instruction decoding unit for decoding the instruction; an operand address calculating unit having an adder and an output latch holding the added result and calculating addresses of plural memory operands, in accordance with address calculation control code outputted from the instruction decoding unit; and an instruction executing unit for executing the instruction, in accordance with the operand address outputted from the operand address calculating unit and an operation control code outputted from the instruction decoding unit; and is capable of executing the plural data operating instruction for processing plural data at high efficiency, by performing address calculation of the plural operands by the operand address calculating unit before executing the instruction by the instruction executing unit.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract: A bit searching circuit includes an offset value designating circuit, a bit position detecting circuit, a count circuit, and a search-end detecting circuit. The offset value designating circuit outputs an offset value indicating a search-start position. The bit position detecting circuit searches for the first bit position which has a first binary value, in a search field between the bit position designated by the offset value and a last bit position in a bit string. The count circuit counts the number of bits in the search field having the first binary value. The search-end detecting circuit detects the end of search processing by subtracting the bit counts detected by the bit position detecting circuit from the count value counted by the count circuit until the result is zero. A data processor using such a bit searching circuit includes a control unit and an instruction execution unit.

Abstract: The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under th

Abstract: An integrated circuit device in which by connecting signal pads of a semiconductor chip to either a power potential lead or a ground potential lead of a package at assembly time, either of plural initial states set in the semiconductor chip in advance is set, and a microprocessor constituted by above-mentioned integrated circuit device in which a signal for setting an initial value of a data bus width control resister at resetting timing is inputted from a data size designating pad and set, and a register for controlling an effective data bus width is provided, and by changing the set value of the data bus width register by the instruction, an effective bit width of the data bus is changed to the value different from the initial set value, thereby the instruction under pre-processing as the pipeline processing is cleared, and the instruction right after is fetched at the effective bus width newly set for execution.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A data processor which comprises a pipeline processing mechanism for executing memory indirect addressing and register indirect addressing in an address calculation stage, checks whether or not an instruction writes an operand to a memory or register, makes each stage of the pipeline mechanism hold reservation information thereof in sequence, thereby reduces the frequency of stops of pipeline processing caused by processing of operand address calculation of the following instruction attending on a writing of the operand of the preceding instruction to a memory or register, so that data processing can be execute at a higher efficiency.

Abstract: The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register.

Abstract: A microprocessor having a test mode wherein a test instruction including an instruction for executing a diagnosing microprogram routine which tests each function block inside of the microprocessor and an instruction which makes data scan in to various latches such as a latch at output portion of the micro ROM for easily diagnosing each internal function blocks by independently operating them, and the latch at the output portion of the micro ROM is allocated an address and is constituted to be loaded in and to store the data from outside of the microprocessor. A diagnosing instruction is loaded from the outside of the microprocessor and the microinstruction of an address allocated the latch is executed, thereby the cause of a fault in the microprocessor can be easily diagnosed.

Abstract: In a data processing system, the program counter (PC) values of coprocessor (CP) instructions are stored in a queue of a CP, and the stored PC value is not erased until the CP has completed executing the instruction. The need for a queue is caused by the pipeline in the CP. Three instructions may be executing concurrently and an exception may occur for any one of them. Accordingly, at least 3 PC values may be stored in the queue. Early overwriting is prevented by making the queue 4 words deep. Also, the CP must assert a CPST signal before accepting a new command from the micro processor (MC). Thus, if the pipeline is full the PST signal will not be asserted and the MP must wait before storing the new PC value in the queue. Instead of the entire PC, only an entry point is transferred to the CP. When only four PC values are saved, the entry point is only two bits and may be transferred along with the command information in a single bus cycle.

Abstract: A microprocessor which incorporates a processor mode using processor instructions for executing pipeline processing of instructions and a test mode using test instructions for easily diagnosing internal function blocks by allowing them to independently operate, and transfers the operation mode to the test mode with holding contents of a plurality of internal registers by test interruption during executing instructions under the processor mode, and then transfers the operation mode to the processor mode with holding the content of the plurality of internal registers by executing a dedicated instruction under the test mode, so that diagnosis of respective function blocks is executed by the test program which reciprocates both modes using the processor instruction and the test instruction.

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract: The data processor of this invention is provided with a multi-stage pipeline processing mechanism which predicts the probability of the branch instruction branching at the instruction decoding stage. The mechanism also detects exceptions at pre-branching and transmits information about a detected exception to the instruction execution stage. If, at the execution stage, it is determined that the branch prediction was incorrect, exception processing is not started. If, at the execution stage, it is determined that the branch prediction was correct, exception processing is started. In this way it is possible to reduce disturbances in pipeline processing for many branch instructions.

Abstract: A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.

Abstract: The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under th

Abstract: A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.

Abstract: A pipeline data processor includes an instruction fetch unit, an instruction decoding unit, an address calculation unit, an operand fetch unit and an instruction operation execution unit. After an instruction, or a part of an instruction, is sent from the instruction fetch unit to the decoding unit, the decoding unit decodes at least a portion of the instruction. For some instructions, the decoding unit outputs two or more step codes to achieve processing of a single operand address. In one embodiment, the operand specifier of the instruction includes a base value and at least one address extension field. The decoding unit outputs a first step code based on the base value and, subsequently, a second step code based on the address extension field. In another embodiment, an operand specifier can include up to an arbitrary number of address extension fields.