Patents by Inventor Toyohiro Harazono

Toyohiro Harazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11883567
    Abstract: Provided herein is a photocatalytic device that is easy to maintain. A photocatalytic device is provided that includes a cabinet, a photocatalytic unit disposed inside the cabinet and including a photocatalyst, a light configured to provide light to the photocatalyst, and a fan configured to send airflow to a surface of the photocatalyst. The photocatalytic unit is configured to be detachable from the cabinet.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: January 30, 2024
    Assignee: KALTECH CORPORATION
    Inventors: Junichi Somei, Kenji Hatazawa, Toyohiro Harazono, Hirohiko Ueda
  • Patent number: 11448245
    Abstract: A wall attachment system is provided that includes an object to be mounted, and an attachment unit for attaching the object to be mounted to a wall surface. The object to be mounted has a back surface installed with a metal. The attachment unit has a front surface installed with a magnet. The wall attachment system is configured so that the metal and the magnet contact each other in response to the object to be mounted being set in position for installation on the attachment unit.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 20, 2022
    Assignee: KALTECH CORPORATION
    Inventors: Junichi Somei, Kenji Hatazawa, Toyohiro Harazono, Hirohiko Ueda
  • Publication number: 20210180624
    Abstract: A wall attachment system is provided that includes an object to be mounted, and an attachment unit for attaching the object to be mounted to a wall surface. The object to be mounted has a back surface installed with a metal. The attachment unit has a front surface installed with a magnet. The wall attachment system is configured so that the metal and the magnet contact each other in response to the object to be mounted being set in position for installation on the attachment unit.
    Type: Application
    Filed: August 19, 2020
    Publication date: June 17, 2021
    Inventors: Junichi SOMEI, Kenji HATAZAWA, Toyohiro HARAZONO, Hirohiko UEDA
  • Publication number: 20210060199
    Abstract: Provided herein is a photocatalytic device that is easy to maintain. A photocatalytic device is provided that includes a cabinet, a photocatalytic unit disposed inside the cabinet and including a photocatalyst, a light configured to provide light to the photocatalyst, and a fan configured to send airflow to a surface of the photocatalyst. The photocatalytic unit is configured to be detachable from the cabinet.
    Type: Application
    Filed: August 19, 2020
    Publication date: March 4, 2021
    Inventors: Junichi SOMEI, Kenji HATAZAWA, Toyohiro HARAZONO, Hirohiko UEDA
  • Patent number: 8482074
    Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Tajiri, Takayoshi Hashimoto, Hisashi Yonemoto, Toyohiro Harazono
  • Publication number: 20120139052
    Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
    Type: Application
    Filed: August 29, 2011
    Publication date: June 7, 2012
    Inventors: Masayuki Tajiri, Takayoshi Hashimoto, Hisashi Yonemoto, Toyohiro Harazono
  • Patent number: 8105894
    Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: January 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Tajiri, Takayoshi Hashimoto, Hisashi Yonemoto, Toyohiro Harazono
  • Publication number: 20110042730
    Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 24, 2011
    Inventors: Masayuki Tajiri, Takayoshi Hashimoto, Hisashi Yonemoto, Toyohiro Harazono
  • Patent number: 5990541
    Abstract: A semiconductor device comprising: a silicon nitride film formed on a semiconductor substrate having a first wiring layer; a first silicon oxide film formed on said silicon nitride film; and a second silicon oxide film formed on said first silicon oxide film by way of an atmospheric pressure CVD process using tetraethyl orthosilicate, siloxane, or disilazane as a source material.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: November 23, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Saito, Toyohiro Harazono