Abstract: The present invention relates to image display apparatuses that use a backlight source. An object of the invention is to provide an image display apparatus including an extra-length absorbing portion that improves the degree of flexibility in routing a lamp cable, which is a power supply path to a light source, and having a high degree of flexibility regarding the position for placing the power supply source. An image display apparatus of the present invention includes an image display panel, a backlight source of the image display panel, a lamp cable which is a power supply path to the light source, and an extra-length absorbing portion that absorbs an extra length of the lamp cable. The extra-length absorbing portion includes a protrusion disposed on a back surface or a side surface of the image display apparatus.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A fault recovery process of a computer is provided for removing a fault from the system as soon as possible, minimizing the secondary fault and improving the availability of the system. In a reliable computer, which includes a system bus, a main memory connected to the system bus, and at least one processing board connected to the system bus, at least one processing board executes the same instructions by n (n>=3) processing units having cache memories respectively. When one of the processing units of the processing board becomes faulty, the other processing units continue executing the processes, which are being executed by the faulty processing board, and then, the processes to be registered in the faulty processing board, are succeeded by other processing boards.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: This invention provides a majority circuit, connecting a plurality of processing units. The majority circuit can detect a single error or multiple errors, and sets the majority output signal to an ineffective level when multiple errors are detected. The majority circuit includes comparators, each comparing two outputs of three processing units, and the error detector recognizes the error status and outputs the single error signal and the multiple error signal accordingly. The majority circuit also includes a selector, which selects the output of a normal processing unit, when the normal processing unit can be specified based on the comparison result. The selector changes the output to a predetermined level, when the normal processing unit cannot be specified.

Abstract: A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.