Abstract: A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.

Abstract: There is provided a semiconductor integrated circuit device provided with a test clock generating circuit which enables high performance test operation and a method of designing a semiconductor integrated circuit device which enables setting of high precision timing margin or the like. The test clock generating circuit provided with a register sequential circuit and a clock output control circuit is provided between the pulse generating circuit and logic circuit. When the test operation is validated, transfer of clock pulse generated in the pulse generating circuit to the logic circuit is stopped and the clock pulse to operate the logic circuit is outputted using the pulse signal generated in the pulse generating circuit by controlling the clock transfer control circuit with the sequential circuit depending on the setting information of register. The test clock generating circuit is comprised with the logic design tool utilizing a computer in order to test the logic circuit function and timing margin.

Abstract: A CMOS LSI stably operates with high speed ECL LSI's to provide a data processing system. Two power sources of a negative ECL operation voltage and a positive CMOS operation voltage are provided. In a CMOS LSI, input signals of ECL level are successively amplified through an ECL input interface having a p-channel differential amplifier and an n-channel type differential amplifier, fed to the CMOS output buffer circuit and converted to the CMOS level, processed in a CMOS internal circuit, and output at the ECL level through output open-drain MOSFETs. The CMOS LSI is operated by two power sources which are level-shifted in correspondence with the ECL signal amplitude, instead of using ground potential and a positive voltage such as VDD.