Patents by Inventor Toyoji Sawada
Toyoji Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207391Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Inventor: Toyoji SAWADA
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Patent number: 11621193Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.Type: GrantFiled: July 22, 2021Date of Patent: April 4, 2023Assignee: SOCIONEXT INC.Inventor: Toyoji Sawada
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Patent number: 11488913Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: GrantFiled: September 29, 2020Date of Patent: November 1, 2022Assignee: Socionext Inc.Inventors: Akio Hara, Toyoji Sawada, Masaki Okuno, Hirosato Ochimizu
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Patent number: 11296013Abstract: A semiconductor wafer includes chip regions; and a scribe region provided between the chip regions, the scribe region extending in a first direction in a plan view, wherein the scribe region includes a first region extending in the first direction, second regions situated on respective sides of the first region in a second direction perpendicular to the first direction in a plan view, each of the two second regions extending in the first direction, and an electrode pad provided in at least the second regions, and each of the two second regions includes one or more trench vias that are wall-shaped, the one or more trench vias extending in the first direction, and at least one trench via of the one or more trench vias having a portion overlapping with the electrode pad in a plan view.Type: GrantFiled: November 24, 2020Date of Patent: April 5, 2022Assignee: SOCIONEXT INC.Inventor: Toyoji Sawada
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Publication number: 20220037206Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.Type: ApplicationFiled: July 22, 2021Publication date: February 3, 2022Inventor: Toyoji SAWADA
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Publication number: 20210166994Abstract: A semiconductor wafer includes chip regions; and a scribe region provided between the chip regions, the scribe region extending in a first direction in a plan view, wherein the scribe region includes a first region extending in the first direction, second regions situated on respective sides of the first region in a second direction perpendicular to the first direction in a plan view, each of the two second regions extending in the first direction, and an electrode pad provided in at least the second regions, and each of the two second regions includes one or more trench vias that are wall-shaped, the one or more trench vias extending in the first direction, and at least one trench via of the one or more trench vias having a portion overlapping with the electrode pad in a plan view.Type: ApplicationFiled: November 24, 2020Publication date: June 3, 2021Inventor: Toyoji SAWADA
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Publication number: 20210028129Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: ApplicationFiled: September 29, 2020Publication date: January 28, 2021Inventors: Akio HARA, Toyoji SAWADA, Masaki OKUNO, Hirosato OCHIMIZU
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Patent number: 8507377Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: GrantFiled: April 21, 2010Date of Patent: August 13, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 8330190Abstract: A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.Type: GrantFiled: March 2, 2010Date of Patent: December 11, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Noriaki Saito, Toyoji Sawada
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Publication number: 20100240211Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: ApplicationFiled: April 21, 2010Publication date: September 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA
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Publication number: 20100224997Abstract: A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Noriaki Saito, Toyoji Sawada
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Patent number: 7755169Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: January 22, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20100133659Abstract: A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film.Type: ApplicationFiled: October 14, 2009Publication date: June 3, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Akio Hara, Toyoji Sawada, Tsuyoshi Koyashiki, Hironori Fukaya
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Publication number: 20090127666Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: January 22, 2009Publication date: May 21, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA, Junichi Mitani
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Patent number: 7498659Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: February 13, 2006Date of Patent: March 3, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 7495309Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.Type: GrantFiled: August 21, 2002Date of Patent: February 24, 2009Assignee: Fujitsu LimitedInventors: Motonobu Sato, Hiroshi Nakadai, Toyoji Sawada, Satoshi Otsuka, Masayuki Nakada
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Publication number: 20070222028Abstract: A silicide region includes a first contact region, a fuse region having a narrower longitudinal width than that of the first contact region, and a second contact region provided on an opposite side of the fuse region with respect to the first contact region. A non-silicide region is provided at a position adjacent to a non-fuse-contacting side that is opposite to a side on which the second contact region in contact with the fuse region.Type: ApplicationFiled: August 4, 2006Publication date: September 27, 2007Applicant: FUJITSU LIMITEDInventors: Yoshihiro Matsuoka, Hideya Matsuyama, Toyoji Sawada, Jun Nagayama, Takashi Suzuki, Masahiro Sueda
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Patent number: 7268433Abstract: A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.Type: GrantFiled: October 24, 2005Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventors: Yoshihiro Matsuoka, Kazuyuki Imamura, Masao Oshima, Takashi Suzuki, Toyoji Sawada
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Publication number: 20070090486Abstract: The fuse comprises an interconnection part 14 luding a silicon layer; a contact part 20b connected one end of the interconnection part 14; and a contact part 20aconnected to the other end of the interconnection part 14 and containing a metal material. A current is flowed from the contact part 20bto the contact part 20a to migrate the metal material of the contact part 20a to the silicon layer to thereby change the contact resistance between the interconnection part 14 and the contact part 20a.Type: ApplicationFiled: January 23, 2006Publication date: April 26, 2007Applicant: FUJITSU LIMITEDInventors: Satoshi Otsuka, Toyoji Sawada, Masato Suga, Jun Nagayama, Motonobu Sato, Takashi Suzuki
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Patent number: 7171592Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.Type: GrantFiled: February 10, 2003Date of Patent: January 30, 2007Assignee: Fujitsu LimitedInventors: Kenji Togashi, Morihiko Hamada, Shigekazu Aoki, Katsumi Shigenobu, Yukio Saka, Yoshikazu Arisaka, Toyoji Sawada, Tadashi Asai