Abstract: A microcomputer includes an operation circuit for performing an operation using a reference voltage. A reference voltage input terminal receives the reference voltage from an external device. An output circuit outputs an output signal from the microcomputer to an external destination. The level of the output signal depends on the reference voltage input through the reference voltage input terminal.

Abstract: A microcomputer incorporating two oscillation circuits for generating clocks having different frequencies, which can be driven even when an oscillator is connected only to one of the oscillation circuits, by counting the number of clock pulses of the first or the second oscillation circuit, and selecting the clock of the first or the second oscillation circuit according to the data latched in a latch circuit that is set by an overflow signal outputted when the count value overflows.

Abstract: A microcomputer in which a voltage drop in a power source is detected by a voltage detecting circuit, and a capacitor is connected to a first power source and/or a second power source on the basis of a detection signal of said detecting circuit thereby to be charged/discharged, so that a reset signal is generated. The supply of a clock signal is controlled on the basis of said detection signal. When a source voltage of the microcomputer is found to be lower than a reference voltage but recovering in a short time, it is possible to resume a programmed operation from a temporary cut-off state without initializing the program.

Abstract: An analog/digital (A/D) converter includes a sequential approximation register (SA register) having a plurality of bits for storing the results of conversion in digits and an incrementor having a smaller number of bits than that of the SA register. The incrementor increments a portion of the results of conversion on the basis of the result of conversion of at least one bit in the SA register so as to minimize an error in the A/D conversion of a smaller number of bits than that of the SA register.

Abstract: A microcomputer comprising a clock circuit which selects a pulse signal as a system clock of the microcomputer from among a plurality of pulse signals and a power source impedance controlling circuit which controls an impedance between a power input terminal and the units of the microcomputer based on the frequency of the pulse signal selected by the clock circuit to provide the electric power to the units of the microcomputer. The power source impedance controlling circuit controls the impedance such that the power source impedance is made lower as the frequency of the selected pulse signal is higher.

Abstract: A dual-port memory is interposed between a host system and a slave system in a multiprocessor system, and data transmission between the host system and the slave system is performed through the dual-port memory using first and second input/output ports, the dual-port memory being accessible from the host system and the slave system simultaneously. An address region of the dual-port memory is placed overlapping the address space of an internal memory of the host system, so that no change is needed in programming in the host system, however, data collision may be generated in a region in the address space shared by the internal memory and the dual-port memory. In order to prevent data collision, the dual-port memory includes a memory cell array having a plurality of memory cells, first cell selection circuitry and second cell selection circuitry, and read data output prohibiting circuitry which prohibits data read out from a selected memory cell from being output to the host system.

Abstract: An analog input is compared with a comparison value by an analog comparator to set a comparison result register and comparison is automatically repeated until the value of the register coincides with the value of an expected value storing register. When the both values coincide with each other, an interrupt request signal is outputted and comparison is completed.

Abstract: To accept a plurality of starting factors without the use of a CPU and improve the real-time processing speed of A/D conversion, the same number of channel selection registers, mode registers and conversion result storage registers as the number of starting factors are provided and divided into groups according to the types of starting factors, and a control circuit for specifying a register group for a starting factor when the factor is generated is also provided.

Abstract: Based on address data of memory cells inputted in a first operating cycle of a host system, data is read from a selected memory cell and outputted from a sense amplifier. At this time, a switch is turned on to allow the output data of the sense amplifiers to be stored in a read storage device. The host system does not accept the data stored in the read storage device and outputted from an A-port data input/output terminal then. Next, the switch is turned off based on address data of the read storage device inputted from the host system in a second operating cycle thereof. In the second operating cycle, the host system accepts the data stored in the read storage device and outputted from the A-port data input/output terminal. In this way, data reading from a memory cell is executed in two operating cycles, and a delay due to the memory cell array and one due to a wiring capacitance of signal lines between the semiconductor memory device and host system are distributed to the respective operating cycles.

Abstract: An analog/digital converter in the present invention compares sequentially with respect to the elapse of time an inputted analog signal with multiple-bit signals corresponding to reference voltages of multiple levels so as to output a digital signal. The analog/digital converter includes a shift register for tracking the termination of the comparisons of each bit signal at every bit with the elapse of time, a selector for sequentially storing in an internal register select shift register bits representing comparison termination signals, and a central processing unit for selecting one of the termination signals stored in the internal register so as to output it to the flag register. The termination signal may be output to the flag register before digital conversion is complete thereby enabling the CPU to prepare to read the final result while digital conversion is still being performed.

Abstract: A counter control method according to the present invention comprising the steps of:(a) allocating switching information corresponding to counters in need of being simultaneously started among switching information each serving to drive a plurality of switching means, to an address (c) of memory means to which operation control means is accessible at a time, and(b) driving said switching means using said switching information so allocated to thereby start said plurality of the counters.

Abstract: A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a "H" level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the "H" level or the "L" level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.