Patents by Inventor Toyokazu Ohnishi

Toyokazu Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100289076
    Abstract: A technique is presented for further reducing on-resistance (or on-voltage) in a vertical semiconductor device provided with a carrier shielding layer. A semiconductor substrate 20 of a semiconductor device 10 comprises a channel section 10A and a non-channel section 10B. An emitter region 26 is formed in the channel section 10A, this emitter region 26 making contact with a side surface of a trench gate 30 and being electrically connected to an emitter electrode 28. The emitter region 26 is not formed in a body region 25 of the non-channel section 10B. In a plan view, an occupied area ratio of the area which a carrier shielding layer 52 located in the non-channel section 10B occupies within the non-channel section 10B is larger than an occupied area ratio of the area which the carrier shielding layer 52 located in the channel section 10A occupies within the channel section 10A.
    Type: Application
    Filed: November 11, 2008
    Publication date: November 18, 2010
    Inventors: Shuichi Nishida, Toyokazu Ohnishi, Tomoyuki Shoji
  • Patent number: 5994725
    Abstract: A semiconductor device having a Schottky gate and a bipolar device. A semiconductor substrate has a surface layer in ohmic contact with the conductor and the deeper layer in Schottky contact with the conductor. The substrate has a recess which reaches into the deeper layer. A conductor field extends from the bottom of the recess in a direction perpendicular to the bottom. Insulating films are formed on both vertical surfaces of the conductor film. Another conductor film is formed across the top of the first conductor film and both insulating films. Conductor films are formed on the surface of the substrate on either side of the insulating films. In this device, the electrode length/width is reduced and the response to the element is improved. Further, because the second conductor film is formed on the first conductor film, it is possible to reduce the gate electrode and the base electrode.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: November 30, 1999
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Toyokazu Ohnishi, Akinori Seki
  • Patent number: 5773334
    Abstract: A semiconductor device is manufactured by a process comprising the steps of forming a cover film on a surface of a semiconductor substrate such that the cover film exposes a portion of the surface, covers a remaining portion thereof and has an edge along a boundary between the exposed portion and the covered portion, forming a first conductor film in a range from the cover film formed in the cover film forming step through the edge to the exposed surface portion of the semiconductor substrate, removing the first conductor film formed in the first conductor film forming step other than a portion formed along the edge such that the first conductor film is left along the edge, forming an insulating film on the opposite sides of the first conductor film left along the edge in the removing step such that a top edge of the left first conductor film is exposed, and forming a second conductor film on the surface of the insulating film formed in the insulating film forming step along the exposed top edge of the first
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: June 30, 1998
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Toyokazu Ohnishi, Akinori Seki
  • Patent number: 5640029
    Abstract: A field-effect transistor has its gate length made to be minute, and a short channel effect is prevented. The field-effect transistor which attains the above objects has first and second semiconductor regions having different impurity concentrations disposed so as to be adjacent to each other. A source electrode is disposed on the second semiconductor region with a high impurity concentration, a drain electrode on the first semiconductor region with a low impurity concentration, and a gate electrode on the first semiconductor region side of the second semiconductor region.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: June 17, 1997
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Toyokazu Ohnishi
  • Patent number: 5604761
    Abstract: A semiconductor laser having a plurality of semiconductor laser chips laminated by solder layers which cause no interference with laser beams is provided. To this end, each of the semiconductor laser chips has a solder sump recess formed in the surface to be soldered at an end adjacent to a laser beam radiating surface and extending through portions of the chip except an active layer.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: February 18, 1997
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Toyokazu Ohnishi, Jiro Nakano, Takahide Sugiyama, Kazuyoshi Tomita, Hiroyuki Kano
  • Patent number: 5553089
    Abstract: A semiconductor laser includes a semiconductor laser chip stack having active layers formed substantially in the central portion thereof in the stacking direction and a pair of opposed reflecting surfaces formed at both ends of the active layers. A convex lens of a light transmissible material fixedly attached to a partially light transmissible reflecting surface of the pair of reflecting surfaces and adapted for converging a laser beam emitted from the partially light transmissible reflecting surface.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: September 3, 1996
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Toyokazu Ohnishi, Jiro Nakano
  • Patent number: 5452316
    Abstract: A semiconductor laser includes a first one-conductive type clad layer, a first active layer, a second other-conductive type clad layer, a third one-conductive type clad layer, a second active layer, and a fourth other-conductive type clad layer stacked in sequence. Either the second other-conductive type clad layer or the third one-conductive type clad layer has a thickness smaller than the thickness of a depletion layer of the p-n junction grown at the boundary between the second other-conductive type clad layer and the third one-conductive type clad layer when voltage is applied across the first one-conductive type clad layer and the fourth other-conductive type clad layer.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: September 19, 1995
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Toyokazu Ohnishi, Jiro Nakano
  • Patent number: 4609903
    Abstract: A thin film resistor for use in microelectronic devices, the resistor having a resistive layer comprising silicon nitride (Si.sub.3 N.sub.4) and refractory metals of tungsten and/or molybdenum. The features of the structure of the resistor is that the film comprises a silicon nitride layer and grains of metal and/or metal silicide, wherein the resistivity is determined mainly by the silicon nitride. Therefore, the total resistance of the resistor can be controlled by controlling the amount of the silicon nitride, thus providing a wide range of the resistivity of 10.sup.-3 to 10.sup.9 .OMEGA.cm. Other characteristics such as immunity to the dopant contained in an adjacent doped layer, namely heat resistivity and low activation energy of the resistivity are verified by associated experiments.
    Type: Grant
    Filed: October 19, 1984
    Date of Patent: September 2, 1986
    Assignee: Fujitsu Limited
    Inventors: Nobuo Toyokura, Toyokazu Ohnishi, Naoki Yokoyama